Loading llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +6 −6 Original line number Diff line number Diff line Loading @@ -10390,7 +10390,7 @@ static bool prepareDAGLevelOperands(ConstraintDecisionInfo &Info, // C_RegisterClass, and a target-defined fashion for // C_Immediate/C_Other). Find a register that we can use. if (OpInfo.AssignedRegs.Regs.empty()) { Info.ErrorMsg << "couldn't allocate output register for " Info.ErrorMsg << "could not allocate output register for " << "constraint '" << OpInfo.ConstraintCode << "'"; return true; } Loading Loading @@ -10420,8 +10420,8 @@ static bool prepareDAGLevelOperands(ConstraintDecisionInfo &Info, if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) { if (OpInfo.isIndirect) { // This happens on gcc/testsuite/gcc.dg/pr8788-1.c Info.ErrorMsg << "inline asm not supported yet: don't know how " << "to handle tied indirect register inputs"; Info.ErrorMsg << "inline asm not supported yet: cannot handle " << "tied indirect register inputs"; return true; } Loading Loading @@ -10552,14 +10552,14 @@ static bool prepareDAGLevelOperands(ConstraintDecisionInfo &Info, // TODO: Support this. if (OpInfo.isIndirect) { Info.ErrorMsg << "Don't know how to handle indirect register inputs " << "yet for constraint '" << OpInfo.ConstraintCode << "'"; Info.ErrorMsg << "cannot handle indirect register inputs yet for " << "constraint '" << OpInfo.ConstraintCode << "'"; return true; } // Copy the input into the appropriate registers. if (OpInfo.AssignedRegs.Regs.empty()) { Info.ErrorMsg << "couldn't allocate input reg for constraint '" Info.ErrorMsg << "could not allocate input reg for constraint '" << OpInfo.ConstraintCode << "'"; return true; } Loading llvm/test/CodeGen/AArch64/aarch64-sve-asm-negative.ll +1 −1 Original line number Diff line number Diff line Loading @@ -5,7 +5,7 @@ ; constraint be used with a Neon register. ; Function Attrs: nounwind readnone ; CHECK: error: couldn't allocate input reg for constraint 'y' ; CHECK: error: could not allocate input reg for constraint 'y' define <4 x i32> @test_neon(<4 x i32> %in1, <4 x i32> %in2) { %1 = tail call <4 x i32> asm "add $0.4s, $1.4s, $2.4s", "=w,w,y"(<4 x i32> %in1, <4 x i32> %in2) ret <4 x i32> %1 Loading llvm/test/CodeGen/AArch64/asm-ld1-wrong-constraint.ll +2 −2 Original line number Diff line number Diff line Loading @@ -11,7 +11,7 @@ define i64 @rdar130887714(ptr noundef %0) { store ptr %0, ptr %2, align 8 %4 = load ptr, ptr %2, align 8 call void asm sideeffect "ld1 { $0.2d, ${0:T}.2d, ${0:U}.2d, ${0:V}.2d} , [$1]", "*w,r"(ptr elementtype(%struct.uint64x2x4_t) %3, ptr %4) #0, !srcloc !0 ; CHECK: error: Don't know how to handle indirect register inputs yet for constraint 'w' at line 250 ; CHECK: error: cannot handle indirect register inputs yet for constraint 'w' at line 250 %5 = getelementptr inbounds %struct.uint64x2x4_t, ptr %3, i32 0, i32 0 %6 = getelementptr inbounds [4 x <2 x i64>], ptr %5, i64 0, i64 0 Loading llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll +3 −3 Original line number Diff line number Diff line Loading @@ -3,9 +3,9 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-gnu" ; CHECK: error: couldn't allocate input reg for constraint 'Upa' ; CHECK: error: couldn't allocate input reg for constraint 'r' ; CHECK: error: couldn't allocate output register for constraint 'w' ; CHECK: error: could not allocate input reg for constraint 'Upa' ; CHECK: error: could not allocate input reg for constraint 'r' ; CHECK: error: could not allocate output register for constraint 'w' ; CHECK: error: unknown token in expression define <vscale x 16 x i1> @foo1(ptr %in) { Loading llvm/test/CodeGen/AArch64/inlineasm-illegal-type.ll +4 −4 Original line number Diff line number Diff line ;RUN: not llc -mtriple=aarch64-linux-gnu -mattr=-fp-armv8 < %s 2>&1 | FileCheck %s ; CHECK: error: couldn't allocate output register for constraint '{d0}' ; CHECK: error: couldn't allocate output register for constraint 'w' ; CHECK: error: couldn't allocate input reg for constraint 'w' ; CHECK: error: couldn't allocate input reg for constraint 'w' ; CHECK: error: could not allocate output register for constraint '{d0}' ; CHECK: error: could not allocate output register for constraint 'w' ; CHECK: error: could not allocate input reg for constraint 'w' ; CHECK: error: could not allocate input reg for constraint 'w' define hidden double @test1(double %xx) local_unnamed_addr #0 { entry: Loading Loading
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +6 −6 Original line number Diff line number Diff line Loading @@ -10390,7 +10390,7 @@ static bool prepareDAGLevelOperands(ConstraintDecisionInfo &Info, // C_RegisterClass, and a target-defined fashion for // C_Immediate/C_Other). Find a register that we can use. if (OpInfo.AssignedRegs.Regs.empty()) { Info.ErrorMsg << "couldn't allocate output register for " Info.ErrorMsg << "could not allocate output register for " << "constraint '" << OpInfo.ConstraintCode << "'"; return true; } Loading Loading @@ -10420,8 +10420,8 @@ static bool prepareDAGLevelOperands(ConstraintDecisionInfo &Info, if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) { if (OpInfo.isIndirect) { // This happens on gcc/testsuite/gcc.dg/pr8788-1.c Info.ErrorMsg << "inline asm not supported yet: don't know how " << "to handle tied indirect register inputs"; Info.ErrorMsg << "inline asm not supported yet: cannot handle " << "tied indirect register inputs"; return true; } Loading Loading @@ -10552,14 +10552,14 @@ static bool prepareDAGLevelOperands(ConstraintDecisionInfo &Info, // TODO: Support this. if (OpInfo.isIndirect) { Info.ErrorMsg << "Don't know how to handle indirect register inputs " << "yet for constraint '" << OpInfo.ConstraintCode << "'"; Info.ErrorMsg << "cannot handle indirect register inputs yet for " << "constraint '" << OpInfo.ConstraintCode << "'"; return true; } // Copy the input into the appropriate registers. if (OpInfo.AssignedRegs.Regs.empty()) { Info.ErrorMsg << "couldn't allocate input reg for constraint '" Info.ErrorMsg << "could not allocate input reg for constraint '" << OpInfo.ConstraintCode << "'"; return true; } Loading
llvm/test/CodeGen/AArch64/aarch64-sve-asm-negative.ll +1 −1 Original line number Diff line number Diff line Loading @@ -5,7 +5,7 @@ ; constraint be used with a Neon register. ; Function Attrs: nounwind readnone ; CHECK: error: couldn't allocate input reg for constraint 'y' ; CHECK: error: could not allocate input reg for constraint 'y' define <4 x i32> @test_neon(<4 x i32> %in1, <4 x i32> %in2) { %1 = tail call <4 x i32> asm "add $0.4s, $1.4s, $2.4s", "=w,w,y"(<4 x i32> %in1, <4 x i32> %in2) ret <4 x i32> %1 Loading
llvm/test/CodeGen/AArch64/asm-ld1-wrong-constraint.ll +2 −2 Original line number Diff line number Diff line Loading @@ -11,7 +11,7 @@ define i64 @rdar130887714(ptr noundef %0) { store ptr %0, ptr %2, align 8 %4 = load ptr, ptr %2, align 8 call void asm sideeffect "ld1 { $0.2d, ${0:T}.2d, ${0:U}.2d, ${0:V}.2d} , [$1]", "*w,r"(ptr elementtype(%struct.uint64x2x4_t) %3, ptr %4) #0, !srcloc !0 ; CHECK: error: Don't know how to handle indirect register inputs yet for constraint 'w' at line 250 ; CHECK: error: cannot handle indirect register inputs yet for constraint 'w' at line 250 %5 = getelementptr inbounds %struct.uint64x2x4_t, ptr %3, i32 0, i32 0 %6 = getelementptr inbounds [4 x <2 x i64>], ptr %5, i64 0, i64 0 Loading
llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll +3 −3 Original line number Diff line number Diff line Loading @@ -3,9 +3,9 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-gnu" ; CHECK: error: couldn't allocate input reg for constraint 'Upa' ; CHECK: error: couldn't allocate input reg for constraint 'r' ; CHECK: error: couldn't allocate output register for constraint 'w' ; CHECK: error: could not allocate input reg for constraint 'Upa' ; CHECK: error: could not allocate input reg for constraint 'r' ; CHECK: error: could not allocate output register for constraint 'w' ; CHECK: error: unknown token in expression define <vscale x 16 x i1> @foo1(ptr %in) { Loading
llvm/test/CodeGen/AArch64/inlineasm-illegal-type.ll +4 −4 Original line number Diff line number Diff line ;RUN: not llc -mtriple=aarch64-linux-gnu -mattr=-fp-armv8 < %s 2>&1 | FileCheck %s ; CHECK: error: couldn't allocate output register for constraint '{d0}' ; CHECK: error: couldn't allocate output register for constraint 'w' ; CHECK: error: couldn't allocate input reg for constraint 'w' ; CHECK: error: couldn't allocate input reg for constraint 'w' ; CHECK: error: could not allocate output register for constraint '{d0}' ; CHECK: error: could not allocate output register for constraint 'w' ; CHECK: error: could not allocate input reg for constraint 'w' ; CHECK: error: could not allocate input reg for constraint 'w' define hidden double @test1(double %xx) local_unnamed_addr #0 { entry: Loading