Commit 5bfe9136 authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r228518: 

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r228518 | tnorthover | 2015-02-07 16:50:47 -0800 (Sat, 07 Feb 2015) | 15 lines

ARM & AArch64: teach LowerVSETCC that output type size may differ from input.

While various DAG combines try to guarantee that a vector SETCC
operation will have the same output size as input, there's nothing
intrinsic to either creation or LegalizeTypes that actually guarantees
it, so the function needs to be ready to handle a mismatch.

Fortunately this is easy enough, just extend or truncate the naturally
compared result.

I couldn't reproduce the failure in other backends that I know have
SIMD, so it's probably only an issue for these two due to shared
heritage.

Should fix PR21645.
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llvm-svn: 228560
parent 8506878b

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

+11 −5
Original line number Diff line number Diff line
@@ -6287,6 +6287,8 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS, 
                                    AArch64CC::CondCode CC, bool NoNans, EVT VT,

                                    SDLoc dl, SelectionDAG &DAG) {

  EVT SrcVT = LHS.getValueType();

  assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&

         "function only supposed to emit natural comparisons");



  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());

  APInt CnstBits(VT.getSizeInBits(), 0);
@@ -6381,13 +6383,15 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op, 
  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();

  SDValue LHS = Op.getOperand(0);

  SDValue RHS = Op.getOperand(1);

  EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();

  SDLoc dl(Op);



  if (LHS.getValueType().getVectorElementType().isInteger()) {

    assert(LHS.getValueType() == RHS.getValueType());

    AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);

    return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),

                                dl, DAG);

    SDValue Cmp =

        EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);

    return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());

  }



  assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
@@ -6401,19 +6405,21 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op, 


  bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;

  SDValue Cmp =

      EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);

      EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);

  if (!Cmp.getNode())

    return SDValue();



  if (CC2 != AArch64CC::AL) {

    SDValue Cmp2 =

        EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);

        EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);

    if (!Cmp2.getNode())

      return SDValue();



    Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);

    Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);

  }



  Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());



  if (ShouldInvert)

    return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());

llvm/lib/Target/ARM/ARMISelLowering.cpp

+16 −13
Original line number Diff line number Diff line
@@ -4487,6 +4487,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 
  SDValue Op0 = Op.getOperand(0);

  SDValue Op1 = Op.getOperand(1);

  SDValue CC = Op.getOperand(2);

  EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();

  EVT VT = Op.getValueType();

  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();

  SDLoc dl(Op);
@@ -4516,8 +4517,8 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 
      TmpOp0 = Op0;

      TmpOp1 = Op1;

      Opc = ISD::OR;

      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);

      Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);

      Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);

      Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);

      break;

    case ISD::SETUO: Invert = true; // Fallthrough

    case ISD::SETO:
@@ -4525,8 +4526,8 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 
      TmpOp0 = Op0;

      TmpOp1 = Op1;

      Opc = ISD::OR;

      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);

      Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);

      Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);

      Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);

      break;

    }

  } else {
@@ -4560,8 +4561,8 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 


      if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {

        Opc = ARMISD::VTST;

        Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));

        Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));

        Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));

        Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));

        Invert = !Invert;

      }

    }
@@ -4587,22 +4588,24 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 
  if (SingleOp.getNode()) {

    switch (Opc) {

    case ARMISD::VCEQ:

      Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;

      Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;

    case ARMISD::VCGE:

      Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;

      Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;

    case ARMISD::VCLEZ:

      Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;

      Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;

    case ARMISD::VCGT:

      Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;

      Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;

    case ARMISD::VCLTZ:

      Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;

      Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;

    default:

      Result = DAG.getNode(Opc, dl, VT, Op0, Op1);

      Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);

    }

  } else {

     Result = DAG.getNode(Opc, dl, VT, Op0, Op1);

     Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);

  }



  Result = DAG.getSExtOrTrunc(Result, dl, VT);



  if (Invert)

    Result = DAG.getNOT(dl, Result, VT);

llvm/test/CodeGen/AArch64/setcc-type-mismatch.ll

0 → 100644
+11 −0
Original line number Diff line number Diff line 
; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s



define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) {

; CHECK-LABEL: test_mismatched_setcc:

; CHECK: cmeq [[CMP128:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s

; CHECK: xtn {{v[0-9]+}}.4h, [[CMP128]].4s



  %tst = icmp eq <4 x i22> %l, %r

  store <4 x i1> %tst, <4 x i1>* %addr

  ret void

}

llvm/test/CodeGen/ARM/setcc-type-mismatch.ll

0 → 100644
+11 −0
Original line number Diff line number Diff line 
; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s



define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) {

; CHECK-LABEL: test_mismatched_setcc:

; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}}

; CHECK: vmovn.i32 {{d[0-9]+}}, [[CMP128]]



  %tst = icmp eq <4 x i22> %l, %r

  store <4 x i1> %tst, <4 x i1>* %addr

  ret void

}