Commit 59df52c5 authored by Krzysztof Parzyszek's avatar Krzysztof Parzyszek
Browse files

Cleanup of the HexagonTargetMachine setup. 

llvm-svn: 181250
parent 70f286d9

llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp

+34 −29
Original line number Diff line number Diff line
@@ -25,13 +25,10 @@ 


using namespace llvm;



static cl::

opt<bool> DisableHardwareLoops(

                        "disable-hexagon-hwloops", cl::Hidden,

                        cl::desc("Disable Hardware Loops for Hexagon target"));

static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",

      cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));



static cl::

opt<bool> DisableHexagonMISched("disable-hexagon-misched",

static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",

      cl::Hidden, cl::ZeroOrMore, cl::init(false),

      cl::desc("Disable Hexagon MI Scheduling"));
@@ -39,6 +36,7 @@ static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt", 
      cl::Hidden, cl::ZeroOrMore, cl::init(false),

      cl::desc("Disable Hexagon CFG Optimization"));





/// HexagonTargetMachineModule - Note that this is used on hosts that

/// cannot link in a library unless there are references into the

/// library.  In particular, it seems that it is not possible to get
@@ -126,55 +124,62 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { 
}



bool HexagonPassConfig::addInstSelector() {

  const HexagonTargetMachine &TM = getHexagonTargetMachine();

  bool NoOpt = (getOptLevel() == CodeGenOpt::None);



  if (getOptLevel() != CodeGenOpt::None)

    addPass(createHexagonRemoveExtendArgs(getHexagonTargetMachine()));

  if (!NoOpt)

    addPass(createHexagonRemoveExtendArgs(TM));



  addPass(createHexagonISelDag(getHexagonTargetMachine(), getOptLevel()));

  addPass(createHexagonISelDag(TM, getOptLevel()));



  if (getOptLevel() != CodeGenOpt::None)

  if (!NoOpt) {

    addPass(createHexagonPeephole());

    printAndVerify("After hexagon peephole pass");

  }



  return false;

}





bool HexagonPassConfig::addPreRegAlloc() {

  if (!DisableHardwareLoops && getOptLevel() != CodeGenOpt::None)

  if (getOptLevel() != CodeGenOpt::None)

    if (!DisableHardwareLoops)

      addPass(createHexagonHardwareLoops());

  return false;

}



bool HexagonPassConfig::addPostRegAlloc() {

  if (!DisableHexagonCFGOpt && getOptLevel() != CodeGenOpt::None)

    addPass(createHexagonCFGOptimizer(getHexagonTargetMachine()));

  return true;

  const HexagonTargetMachine &TM = getHexagonTargetMachine();

  if (getOptLevel() != CodeGenOpt::None)

    if (!DisableHexagonCFGOpt)

      addPass(createHexagonCFGOptimizer(TM));

  return false;

}





bool HexagonPassConfig::addPreSched2() {

  if (getOptLevel() != CodeGenOpt::None)

    addPass(&IfConverterID);

  return true;

  return false;

}



bool HexagonPassConfig::addPreEmitPass() {

  const HexagonTargetMachine &TM = getHexagonTargetMachine();

  bool NoOpt = (getOptLevel() == CodeGenOpt::None);



  if (!DisableHardwareLoops && getOptLevel() != CodeGenOpt::None)

    addPass(createHexagonFixupHwLoops());



  if (getOptLevel() != CodeGenOpt::None)

  if (!NoOpt)

    addPass(createHexagonNewValueJump());



  // Expand Spill code for predicate registers.

  addPass(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));

  addPass(createHexagonExpandPredSpillCode(TM));



  // Split up TFRcondsets into conditional transfers.

  addPass(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));

  addPass(createHexagonSplitTFRCondSets(TM));



  // Create Packets.

  if (getOptLevel() != CodeGenOpt::None)

  if (!NoOpt) {

    if (!DisableHardwareLoops)

      addPass(createHexagonFixupHwLoops());

    addPass(createHexagonPacketizer());

  }



  return false;

}