Commit 599591f3 authored by Petar Avramovic's avatar Petar Avramovic
Browse files

[MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store 

Add vector MSA register classes to fprb, they are 128 bit wide.
MSA instructions use the same registers for both integer and floating
point operations. Therefore we only need to check for vector element
size during legalization or instruction selection.

Add helper function in MipsLegalizerInfo and switch to legalIf
LegalizeRuleSet to keep legalization rules compact since they depend
on MipsSubtarget and presence of MSA.
fprb is assigned to all vector operands.
Move selectLoadStoreOpCode to MipsInstructionSelector in order to
reduce number of arguments.

Differential Revision: https://reviews.llvm.org/D68867

llvm-svn: 374872
parent d46ac44e

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

+27 −17
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ private: 
  const TargetRegisterClass *

  getRegClassForTypeOnBank(unsigned OpSize, const RegisterBank &RB,

                           const RegisterBankInfo &RBI) const;

  unsigned selectLoadStoreOpCode(MachineInstr &I,

                                 MachineRegisterInfo &MRI) const;



  const MipsTargetMachine &TM;

  const MipsSubtarget &STI;
@@ -159,9 +161,15 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm, 
}



/// Returning Opc indicates that we failed to select MIPS instruction opcode.

static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes,

                                      unsigned RegBank, bool isFP64) {

  bool isStore = Opc == TargetOpcode::G_STORE;

unsigned

MipsInstructionSelector::selectLoadStoreOpCode(MachineInstr &I,

                                               MachineRegisterInfo &MRI) const {

  STI.getRegisterInfo();

  const Register DestReg = I.getOperand(0).getReg();

  const unsigned RegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();

  const unsigned MemSizeInBytes = (*I.memoperands_begin())->getSize();

  unsigned Opc = I.getOpcode();

  const bool isStore = Opc == TargetOpcode::G_STORE;

  if (RegBank == Mips::GPRBRegBankID) {

    if (isStore)

      switch (MemSizeInBytes) {
@@ -193,10 +201,24 @@ static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes, 
    case 4:

      return isStore ? Mips::SWC1 : Mips::LWC1;

    case 8:

      if (isFP64)

      if (STI.isFP64bit())

        return isStore ? Mips::SDC164 : Mips::LDC164;

      else

        return isStore ? Mips::SDC1 : Mips::LDC1;

    case 16: {

      assert(STI.hasMSA() && "Vector instructions require target with MSA.");

      const unsigned VectorElementSizeInBytes =

          MRI.getType(DestReg).getElementType().getSizeInBytes();

      if (VectorElementSizeInBytes == 1)

        return isStore ? Mips::ST_B : Mips::LD_B;

      if (VectorElementSizeInBytes == 2)

        return isStore ? Mips::ST_H : Mips::LD_H;

      if (VectorElementSizeInBytes == 4)

        return isStore ? Mips::ST_W : Mips::LD_W;

      if (VectorElementSizeInBytes == 8)

        return isStore ? Mips::ST_D : Mips::LD_D;

      return Opc;

    }

    default:

      return Opc;

    }
@@ -361,19 +383,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { 
  case G_LOAD:

  case G_ZEXTLOAD:

  case G_SEXTLOAD: {

    const Register DestReg = I.getOperand(0).getReg();

    const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();

    const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();

    const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize();



    if (DestRegBank == Mips::GPRBRegBankID && OpSize != 32)

      return false;



    if (DestRegBank == Mips::FPRBRegBankID && OpSize != 32 && OpSize != 64)

      return false;



    const unsigned NewOpc = selectLoadStoreOpCode(

        I.getOpcode(), OpMemSizeInBytes, DestRegBank, STI.isFP64bit());

    const unsigned NewOpc = selectLoadStoreOpCode(I, MRI);

    if (NewOpc == I.getOpcode())

      return false;

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

+44 −5
Original line number Diff line number Diff line
@@ -16,12 +16,41 @@ 


using namespace llvm;



struct TypesAndMemOps {

  LLT ValTy;

  LLT PtrTy;

  unsigned MemSize;

  bool MustBeNaturallyAligned;

};



static bool

CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,

                        std::initializer_list<TypesAndMemOps> SupportedValues) {

  for (auto &Val : SupportedValues) {

    if (Val.ValTy != Query.Types[0])

      continue;

    if (Val.PtrTy != Query.Types[1])

      continue;

    if (Val.MemSize != Query.MMODescrs[0].SizeInBits)

      continue;

    if (Val.MustBeNaturallyAligned &&

        Query.MMODescrs[0].SizeInBits % Query.MMODescrs[0].AlignInBits != 0)

      continue;

    return true;

  }

  return false;

}



MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {

  using namespace TargetOpcode;



  const LLT s1 = LLT::scalar(1);

  const LLT s32 = LLT::scalar(32);

  const LLT s64 = LLT::scalar(64);

  const LLT v16s8 = LLT::vector(16, 8);

  const LLT v8s16 = LLT::vector(8, 16);

  const LLT v4s32 = LLT::vector(4, 32);

  const LLT v2s64 = LLT::vector(2, 64);

  const LLT p0 = LLT::pointer(0, 32);



  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
@@ -36,11 +65,21 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { 
      .maxScalar(0, s32);



  getActionDefinitionsBuilder({G_LOAD, G_STORE})

      .legalForTypesWithMemDesc({{s32, p0, 8, 8},

                                 {s32, p0, 16, 8},

                                 {s32, p0, 32, 8},

                                 {s64, p0, 64, 8},

                                 {p0, p0, 32, 8}})

      .legalIf([=, &ST](const LegalityQuery &Query) {

        if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()},

                                            {s32, p0, 16, ST.hasMips32r6()},

                                            {s32, p0, 32, ST.hasMips32r6()},

                                            {p0, p0, 32, ST.hasMips32r6()},

                                            {s64, p0, 64, ST.hasMips32r6()}}))

          return true;

        if (ST.hasMSA() &&

            CheckTy0Ty1MemSizeAlign(Query, {{v16s8, p0, 128, false},

                                            {v8s16, p0, 128, false},

                                            {v4s32, p0, 128, false},

                                            {v2s64, p0, 128, false}}))

          return true;

        return false;

      })

      .minScalar(0, s32);



  getActionDefinitionsBuilder(G_IMPLICIT_DEF)

llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

+31 −3
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 


#include "MipsRegisterBankInfo.h"

#include "MipsInstrInfo.h"

#include "MipsTargetMachine.h"

#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"

#include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"

#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
@@ -27,20 +28,23 @@ enum PartialMappingIdx { 
  PMI_GPR,

  PMI_SPR,

  PMI_DPR,

  PMI_MSA,

  PMI_Min = PMI_GPR,

};



RegisterBankInfo::PartialMapping PartMappings[]{

    {0, 32, GPRBRegBank},

    {0, 32, FPRBRegBank},

    {0, 64, FPRBRegBank}

    {0, 64, FPRBRegBank},

    {0, 128, FPRBRegBank}

};



enum ValueMappingIdx {

    InvalidIdx = 0,

    GPRIdx = 1,

    SPRIdx = 4,

    DPRIdx = 7

    DPRIdx = 7,

    MSAIdx = 10

};



RegisterBankInfo::ValueMapping ValueMappings[] = {
@@ -57,7 +61,11 @@ RegisterBankInfo::ValueMapping ValueMappings[] = { 
    // up to 3 operands in FPRs - double precission

    {&PartMappings[PMI_DPR - PMI_Min], 1},

    {&PartMappings[PMI_DPR - PMI_Min], 1},

    {&PartMappings[PMI_DPR - PMI_Min], 1}

    {&PartMappings[PMI_DPR - PMI_Min], 1},

    // up to 3 operands in FPRs - MSA

    {&PartMappings[PMI_MSA - PMI_Min], 1},

    {&PartMappings[PMI_MSA - PMI_Min], 1},

    {&PartMappings[PMI_MSA - PMI_Min], 1}

};



} // end namespace Mips
@@ -86,6 +94,10 @@ const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass( 
  case Mips::FGR32RegClassID:

  case Mips::FGR64RegClassID:

  case Mips::AFGR64RegClassID:

  case Mips::MSA128BRegClassID:

  case Mips::MSA128HRegClassID:

  case Mips::MSA128WRegClassID:

  case Mips::MSA128DRegClassID:

    return getRegBank(Mips::FPRBRegBankID);

  default:

    llvm_unreachable("Register class not supported");
@@ -355,6 +367,13 @@ void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction( 
  }

}



static const MipsRegisterBankInfo::ValueMapping *

getMSAMapping(const MachineFunction &MF) {

  assert(static_cast<const MipsSubtarget &>(MF.getSubtarget()).hasMSA() &&

         "MSA mapping not available on target without MSA.");

  return &Mips::ValueMappings[Mips::MSAIdx];

}



static const MipsRegisterBankInfo::ValueMapping *getFprbMapping(unsigned Size) {

  return Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]

                    : &Mips::ValueMappings[Mips::DPRIdx];
@@ -406,6 +425,9 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
      if (RegTy.isScalar() &&

          (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64))

        return getInvalidInstructionMapping();



      if (RegTy.isVector() && RegTy.getSizeInBits() != 128)

        return getInvalidInstructionMapping();

    }

  }
@@ -440,6 +462,12 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
    break;

  case G_STORE:

  case G_LOAD:

    if (Op0Size == 128) {

      OperandsMapping = getOperandsMapping(

          {getMSAMapping(MF), &Mips::ValueMappings[Mips::GPRIdx]});

      break;

    }



    if (!Op0Ty.isPointer())

      InstTy = TI.determineInstType(&MI);

llvm/lib/Target/Mips/MipsRegisterBanks.td

+1 −1
Original line number Diff line number Diff line
@@ -11,4 +11,4 @@ 


def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;



def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64]>;
 
def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64, MSA128D]>;

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir

0 → 100644
+156 −0
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600

--- |



  define void @load_store_v16i8(<16 x i8>* %a, <16 x i8>* %b) { entry: ret void }

  define void @load_store_v8i16(<8 x i16>* %a, <8 x i16>* %b) { entry: ret void }

  define void @load_store_v4i32(<4 x i32>* %a, <4 x i32>* %b) { entry: ret void }

  define void @load_store_v2i64(<2 x i64>* %a, <2 x i64>* %b) { entry: ret void }

  define void @load_store_v4f32(<4 x float>* %a, <4 x float>* %b) { entry: ret void }

  define void @load_store_v2f64(<2 x double>* %a, <2 x double>* %b) { entry: ret void }



...

---

name:            load_store_v16i8

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  bb.1.entry:

    liveins: $a0, $a1



    ; P5600-LABEL: name: load_store_v16i8

    ; P5600: liveins: $a0, $a1

    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0

    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1

    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)

    ; P5600: ST_B [[LD_B]], [[COPY]], 0 :: (store 16 into %ir.a)

    ; P5600: RetRA

    %0:gprb(p0) = COPY $a0

    %1:gprb(p0) = COPY $a1

    %2:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)

    G_STORE %2(<16 x s8>), %0(p0) :: (store 16 into %ir.a)

    RetRA



...

---

name:            load_store_v8i16

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  bb.1.entry:

    liveins: $a0, $a1



    ; P5600-LABEL: name: load_store_v8i16

    ; P5600: liveins: $a0, $a1

    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0

    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1

    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)

    ; P5600: ST_H [[LD_H]], [[COPY]], 0 :: (store 16 into %ir.a)

    ; P5600: RetRA

    %0:gprb(p0) = COPY $a0

    %1:gprb(p0) = COPY $a1

    %2:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)

    G_STORE %2(<8 x s16>), %0(p0) :: (store 16 into %ir.a)

    RetRA



...

---

name:            load_store_v4i32

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  bb.1.entry:

    liveins: $a0, $a1



    ; P5600-LABEL: name: load_store_v4i32

    ; P5600: liveins: $a0, $a1

    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0

    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1

    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)

    ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store 16 into %ir.a)

    ; P5600: RetRA

    %0:gprb(p0) = COPY $a0

    %1:gprb(p0) = COPY $a1

    %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)

    G_STORE %2(<4 x s32>), %0(p0) :: (store 16 into %ir.a)

    RetRA



...

---

name:            load_store_v2i64

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  bb.1.entry:

    liveins: $a0, $a1



    ; P5600-LABEL: name: load_store_v2i64

    ; P5600: liveins: $a0, $a1

    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0

    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1

    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)

    ; P5600: ST_D [[LD_D]], [[COPY]], 0 :: (store 16 into %ir.a)

    ; P5600: RetRA

    %0:gprb(p0) = COPY $a0

    %1:gprb(p0) = COPY $a1

    %2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)

    G_STORE %2(<2 x s64>), %0(p0) :: (store 16 into %ir.a)

    RetRA



...

---

name:            load_store_v4f32

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  bb.1.entry:

    liveins: $a0, $a1



    ; P5600-LABEL: name: load_store_v4f32

    ; P5600: liveins: $a0, $a1

    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0

    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1

    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)

    ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store 16 into %ir.a)

    ; P5600: RetRA

    %0:gprb(p0) = COPY $a0

    %1:gprb(p0) = COPY $a1

    %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)

    G_STORE %2(<4 x s32>), %0(p0) :: (store 16 into %ir.a)

    RetRA



...

---

name:            load_store_v2f64

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  bb.1.entry:

    liveins: $a0, $a1



    ; P5600-LABEL: name: load_store_v2f64

    ; P5600: liveins: $a0, $a1

    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0

    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1

    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)

    ; P5600: ST_D [[LD_D]], [[COPY]], 0 :: (store 16 into %ir.a)

    ; P5600: RetRA

    %0:gprb(p0) = COPY $a0

    %1:gprb(p0) = COPY $a1

    %2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)

    G_STORE %2(<2 x s64>), %0(p0) :: (store 16 into %ir.a)

    RetRA



...