Commit 57987c5f authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r260495: 

------------------------------------------------------------------------
r260495 | Matthew.Arsenault | 2016-02-10 22:15:39 -0800 (Wed, 10 Feb 2016) | 9 lines

AMDGPU: Fix constant bus use check with subregisters

If the two operands to an instruction were both
subregisters of the same super register, it would incorrectly
think this counted as the same constant bus use.

This fixes the verifier error in fmin_legacy.ll which
was missing -verify-machineinstrs.

------------------------------------------------------------------------

llvm-svn: 271640
parent 2c04ddab

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+8 −4
Original line number Diff line number Diff line
@@ -1807,7 +1807,7 @@ bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI, 
bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,

                                 const MachineOperand *MO) const {

  const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();

  const MCInstrDesc &InstDesc = get(MI->getOpcode());

  const MCInstrDesc &InstDesc = MI->getDesc();

  const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];

  const TargetRegisterClass *DefinedRC =

      OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
@@ -1816,13 +1816,17 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx, 


  if (isVALU(*MI) &&

      usesConstantBus(MRI, *MO, DefinedRC->getSize())) {

    unsigned SGPRUsed =

        MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;



    RegSubRegPair SGPRUsed;

    if (MO->isReg())

      SGPRUsed = RegSubRegPair(MO->getReg(), MO->getSubReg());



    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {

      if (i == OpIdx)

        continue;

      const MachineOperand &Op = MI->getOperand(i);

      if (Op.isReg() && Op.getReg() != SGPRUsed &&

      if (Op.isReg() &&

          (Op.getReg() != SGPRUsed.Reg || Op.getSubReg() != SGPRUsed.SubReg) &&

          usesConstantBus(MRI, Op, getOpSize(*MI, i))) {

        return false;

      }

llvm/test/CodeGen/AMDGPU/fmax_legacy.ll

+2 −2
Original line number Diff line number Diff line 
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s

; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s

; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s



; FIXME: Should replace unsafe-fp-math with no signed zeros.

llvm/test/CodeGen/AMDGPU/fmin_legacy.ll

+27 −6
Original line number Diff line number Diff line 
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s

; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math  -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s

; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s



; FIXME: Should replace unsafe-fp-math with no signed zeros.



declare i32 @llvm.r600.read.tidig.x() #1



; FUNC-LABEL: @test_fmin_legacy_f32

; The two inputs to the instruction are different SGPRs from the same

; super register, so we can't fold both SGPR operands even though they

; are both the same register.



; FUNC-LABEL: {{^}}s_test_fmin_legacy_subreg_inputs_f32:

; EG: MIN *

; SI-SAFE: v_min_legacy_f32_e64

; SI-NONAN: v_min_f32_e64

define void @test_fmin_legacy_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 {

; SI-SAFE: v_min_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}

; SI-NONAN: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}

define void @s_test_fmin_legacy_subreg_inputs_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 {

   %r0 = extractelement <4 x float> %reg0, i32 0

   %r1 = extractelement <4 x float> %reg0, i32 1

   %r2 = fcmp uge float %r0, %r1
@@ -20,6 +24,23 @@ define void @test_fmin_legacy_f32(<4 x float> addrspace(1)* %out, <4 x float> in 
   ret void

}



; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32:

; SI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb

; SI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc



; SI-SAFE-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]]

; SI-NONAN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]



; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[VA]]

; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[VB]]



define void @s_test_fmin_legacy_ule_f32(float addrspace(1)* %out, float %a, float %b) #0 {

  %cmp = fcmp ule float %a, %b

  %val = select i1 %cmp, float %a, float %b

  store float %val, float addrspace(1)* %out, align 4

  ret void

}



; FUNC-LABEL: @test_fmin_legacy_ule_f32

; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}

; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4