Loading lldb/test/Shell/ScriptInterpreter/Python/command_relative_import.test +2 −2 Original line number Diff line number Diff line Loading @@ -8,9 +8,9 @@ # RUN: -o 'command source %t/foo/magritte.in' \ # RUN: -o 'command source %t/foo/zip.in' \ # RUN: -o 'command source %t/foo/magritte.in' \ # RUN; -o 'zip' \ # RUN: -o 'zip' \ # RUN: -o 'hello' # RUN -o 'magritte' 2>&1 | FileCheck %s # RUN: -o 'magritte' 2>&1 | FileCheck %s # The first time importing 'magritte' fails because we didn't pass -c. # CHECK: ModuleNotFoundError: No module named 'magritte' Loading llvm/test/Bitcode/attributes.ll +1 −1 Original line number Diff line number Diff line Loading @@ -404,7 +404,7 @@ define void @f68() mustprogress ret void } ; CHECK; define void @f69() #42 ; CHECK: define void @f69() #42 define void @f69() nocallback { ret void Loading llvm/test/CodeGen/AArch64/cmp-to-cmn.ll +2 −2 Original line number Diff line number Diff line Loading @@ -125,7 +125,7 @@ define i1 @test_EQ_IssEbT(i16 %a, i16 %b) { ; CHECK: sxth w8, w1 ; CHECK-NEXT: cmn w8, w0, sxth ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT; ret ; CHECK-NEXT: ret entry: %conv = sext i16 %a to i32 %conv1 = sext i16 %b to i32 Loading @@ -139,7 +139,7 @@ define i1 @test_EQ_IscEbT(i16 %a, i8 %b) { ; CHECK: and w8, w1, #0xff ; CHECK-NEXT: cmn w8, w0, sxth ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT; ret ; CHECK-NEXT: ret entry: %conv = sext i16 %a to i32 %conv1 = zext i8 %b to i32 Loading llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll +1 −1 Original line number Diff line number Diff line Loading @@ -97,7 +97,7 @@ ; GCN: ; %Flow5 ; GCN-NEXT: s_or_b64 exec, exec, ; GCN-NEXT; s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[EXIT0]] ; GCN-NEXT: s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[EXIT0]] ; GCN: ; %exit0 ; GCN: buffer_store_dword Loading llvm/test/CodeGen/ARM/no-fpscr-liveness.ll +1 −1 Original line number Diff line number Diff line Loading @@ -14,7 +14,7 @@ target triple = "thumbv7s-apple-ios" ; VMRS instruction comes before any other instruction writing FPSCR: ; CHECK-NOT: vcmp ; CHECK: vmrs {{r[0-9]}}, fpscr ; CHECK; vcmp ; CHECK: vcmp ; ... ; CHECK: add sp, #8 ; CHECK: bx lr Loading Loading
lldb/test/Shell/ScriptInterpreter/Python/command_relative_import.test +2 −2 Original line number Diff line number Diff line Loading @@ -8,9 +8,9 @@ # RUN: -o 'command source %t/foo/magritte.in' \ # RUN: -o 'command source %t/foo/zip.in' \ # RUN: -o 'command source %t/foo/magritte.in' \ # RUN; -o 'zip' \ # RUN: -o 'zip' \ # RUN: -o 'hello' # RUN -o 'magritte' 2>&1 | FileCheck %s # RUN: -o 'magritte' 2>&1 | FileCheck %s # The first time importing 'magritte' fails because we didn't pass -c. # CHECK: ModuleNotFoundError: No module named 'magritte' Loading
llvm/test/Bitcode/attributes.ll +1 −1 Original line number Diff line number Diff line Loading @@ -404,7 +404,7 @@ define void @f68() mustprogress ret void } ; CHECK; define void @f69() #42 ; CHECK: define void @f69() #42 define void @f69() nocallback { ret void Loading
llvm/test/CodeGen/AArch64/cmp-to-cmn.ll +2 −2 Original line number Diff line number Diff line Loading @@ -125,7 +125,7 @@ define i1 @test_EQ_IssEbT(i16 %a, i16 %b) { ; CHECK: sxth w8, w1 ; CHECK-NEXT: cmn w8, w0, sxth ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT; ret ; CHECK-NEXT: ret entry: %conv = sext i16 %a to i32 %conv1 = sext i16 %b to i32 Loading @@ -139,7 +139,7 @@ define i1 @test_EQ_IscEbT(i16 %a, i8 %b) { ; CHECK: and w8, w1, #0xff ; CHECK-NEXT: cmn w8, w0, sxth ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT; ret ; CHECK-NEXT: ret entry: %conv = sext i16 %a to i32 %conv1 = zext i8 %b to i32 Loading
llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll +1 −1 Original line number Diff line number Diff line Loading @@ -97,7 +97,7 @@ ; GCN: ; %Flow5 ; GCN-NEXT: s_or_b64 exec, exec, ; GCN-NEXT; s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[EXIT0]] ; GCN-NEXT: s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[EXIT0]] ; GCN: ; %exit0 ; GCN: buffer_store_dword Loading
llvm/test/CodeGen/ARM/no-fpscr-liveness.ll +1 −1 Original line number Diff line number Diff line Loading @@ -14,7 +14,7 @@ target triple = "thumbv7s-apple-ios" ; VMRS instruction comes before any other instruction writing FPSCR: ; CHECK-NOT: vcmp ; CHECK: vmrs {{r[0-9]}}, fpscr ; CHECK; vcmp ; CHECK: vcmp ; ... ; CHECK: add sp, #8 ; CHECK: bx lr Loading