Commit 572dde55 authored by jasonliu's avatar jasonliu
Browse files

[XCOFF][AIX] Use 'L..' instead of '.L' for getPrivateGlobalPrefix in DataLayout 

Summary:
D80831 changed part of the prefix usage for AIX.
But there are other places getting prefix from DataLayout.
This patch intends to make prefix usage consistent on AIX.

Reviewed by: hubert.reinterpretcast, daltenty

Differential Revision: https://reviews.llvm.org/D81270
parent fc81f48f

clang/lib/Basic/Targets/PPC.h

+9 −5
Original line number Diff line number Diff line
@@ -349,6 +349,9 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 
public:

  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)

      : PPCTargetInfo(Triple, Opts) {

    if (Triple.isOSAIX())

      resetDataLayout("E-m:a-p:32:32-i64:64-n32");

    else

      resetDataLayout("E-m:e-p:32:32-i64:64-n32");



    switch (getTriple().getOS()) {
@@ -395,7 +398,11 @@ public: 
    IntMaxType = SignedLong;

    Int64Type = SignedLong;



    if ((Triple.getArch() == llvm::Triple::ppc64le)) {

    if (Triple.isOSAIX()) {

      // TODO: Set appropriate ABI for AIX platform.

      resetDataLayout("E-m:a-i64:64-n32:64");

      SuitableAlign = 64;

    } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {

      resetDataLayout("e-m:e-i64:64-n32:64");

      ABI = "elfv2";

    } else {
@@ -403,9 +410,6 @@ public: 
      ABI = "elfv1";

    }



    if (Triple.getOS() == llvm::Triple::AIX)

      SuitableAlign = 64;



    if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX ||

        Triple.isMusl()) {

      LongDoubleWidth = LongDoubleAlign = 64;

llvm/docs/LangRef.rst

+1 −0
Original line number Diff line number Diff line
@@ -2366,6 +2366,7 @@ as follows: 
      starting with ``?`` are not mangled in any way.

    * ``w``: Windows COFF mangling: Similar to ``x``, except that normal C

      symbols do not receive a ``_`` prefix.

    * ``a``: XCOFF mangling: Private symbols get a ``L..`` prefix.

``n<size1>:<size2>:<size3>...``

    This specifies a set of native integer widths for the target CPU in

    bits. For example, it might contain ``n32`` for 32-bit PowerPC,

llvm/include/llvm/IR/DataLayout.h

+5 −1
Original line number Diff line number Diff line
@@ -133,7 +133,8 @@ private: 
    MM_MachO,

    MM_WinCOFF,

    MM_WinCOFFX86,

    MM_Mips

    MM_Mips,

    MM_XCOFF

  };

  ManglingModeT ManglingMode;
@@ -309,6 +310,7 @@ public: 
    case MM_ELF:

    case MM_Mips:

    case MM_WinCOFF:

    case MM_XCOFF:

      return '\0';

    case MM_MachO:

    case MM_WinCOFFX86:
@@ -329,6 +331,8 @@ public: 
    case MM_MachO:

    case MM_WinCOFFX86:

      return "L";

    case MM_XCOFF:

      return "L..";

    }

    llvm_unreachable("invalid mangling mode");

  }

llvm/lib/IR/DataLayout.cpp

+5 −0
Original line number Diff line number Diff line
@@ -153,6 +153,8 @@ const char *DataLayout::getManglingComponent(const Triple &T) { 
    return "-m:o";

  if (T.isOSWindows() && T.isOSBinFormatCOFF())

    return T.getArch() == Triple::x86 ? "-m:x" : "-m:w";

  if (T.isOSBinFormatXCOFF())

    return "-m:a";

  return "-m:e";

}
@@ -444,6 +446,9 @@ void DataLayout::parseSpecifier(StringRef Desc) { 
      case 'x':

        ManglingMode = MM_WinCOFFX86;

        break;

      case 'a':

        ManglingMode = MM_XCOFF;

        break;

      }

      break;

    default:

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

+5 −5
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ entry: 


; 32SMALL-ASM:         .csect .rodata[RO],2

; 32SMALL-ASM:         .align  2

; 32SMALL-ASM: .LCPI0_0:

; 32SMALL-ASM: L..CPI0_0:

; 32SMALL-ASM:         .vbyte	4, 0x40b00000

; 32SMALL-ASM: .test_float:

; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], L..C0(2)
@@ -56,7 +56,7 @@ entry: 


; 32LARGE-ASM:         .csect .rodata[RO],2

; 32LARGE-ASM:         .align  2

; 32LARGE-ASM: .LCPI0_0:

; 32LARGE-ASM: L..CPI0_0:

; 32LARGE-ASM:         .vbyte	4, 0x40b00000

; 32LARGE-ASM: .test_float:

; 32LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
@@ -66,7 +66,7 @@ entry: 


; 64SMALL-ASM:         .csect .rodata[RO],2

; 64SMALL-ASM:         .align  2

; 64SMALL-ASM: .LCPI0_0:

; 64SMALL-ASM: L..CPI0_0:

; 64SMALL-ASM:         .vbyte	4, 0x40b00000

; 64SMALL-ASM: .test_float:

; 64SMALL-ASM:         ld [[REG1:[0-9]+]], L..C0(2)
@@ -75,7 +75,7 @@ entry: 


; 64LARGE-ASM:         .csect .rodata[RO],2

; 64LARGE-ASM:         .align  2

; 64LARGE-ASM: .LCPI0_0:

; 64LARGE-ASM: L..CPI0_0:

; 64LARGE-ASM:         .vbyte	4, 0x40b00000

; 64LARGE-ASM: .test_float:

; 64LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
@@ -84,4 +84,4 @@ entry: 
; 64LARGE-ASM:         blr



; CHECK: .toc

; CHECK: .tc .LCPI0_0[TC],.LCPI0_0
 
; CHECK: .tc L..CPI0_0[TC],L..CPI0_0