Commit 534d8866 authored by Sameer Sahasrabuddhe's avatar Sameer Sahasrabuddhe
Browse files

[AMDGPU] add generated checks for some LIT tests

This is in prepration for further changes that affect these tests.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D75403
parent 6f029dad
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+57 −0
Original line number Diff line number Diff line
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; NOTE: The checks for opt are NOT added by the update script. Those
;       checks are looking for the absence of specific metadata, which
;       cannot be expressed reliably by the generated checks.

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ISA
; RUN: opt --amdgpu-annotate-uniform -S %s |  FileCheck %s -check-prefix=UNIFORM
; RUN: opt --amdgpu-annotate-uniform --si-annotate-control-flow -S %s |  FileCheck %s -check-prefix=CONTROLFLOW

@@ -9,6 +16,56 @@
target triple = "amdgcn-mesa-mesa3d"

define amdgpu_ps void @main(i32 %0, float %1) {
; ISA-LABEL: main:
; ISA:       ; %bb.0: ; %start
; ISA-NEXT:    v_readfirstlane_b32 s0, v0
; ISA-NEXT:    s_mov_b32 m0, s0
; ISA-NEXT:    s_mov_b32 s0, 0
; ISA-NEXT:    v_interp_p1_f32_e32 v0, v1, attr0.x
; ISA-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0
; ISA-NEXT:    s_mov_b64 s[2:3], 0
; ISA-NEXT:    ; implicit-def: $sgpr6_sgpr7
; ISA-NEXT:    ; implicit-def: $sgpr4_sgpr5
; ISA-NEXT:    s_branch BB0_3
; ISA-NEXT:  BB0_1: ; %Flow1
; ISA-NEXT:    ; in Loop: Header=BB0_3 Depth=1
; ISA-NEXT:    s_or_b64 exec, exec, s[8:9]
; ISA-NEXT:    s_add_i32 s0, s0, 1
; ISA-NEXT:    s_mov_b64 s[8:9], 0
; ISA-NEXT:  BB0_2: ; %Flow
; ISA-NEXT:    ; in Loop: Header=BB0_3 Depth=1
; ISA-NEXT:    s_and_b64 s[10:11], exec, s[6:7]
; ISA-NEXT:    s_or_b64 s[2:3], s[10:11], s[2:3]
; ISA-NEXT:    s_andn2_b64 s[4:5], s[4:5], exec
; ISA-NEXT:    s_and_b64 s[8:9], s[8:9], exec
; ISA-NEXT:    s_or_b64 s[4:5], s[4:5], s[8:9]
; ISA-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; ISA-NEXT:    s_cbranch_execz BB0_6
; ISA-NEXT:  BB0_3: ; %loop
; ISA-NEXT:    ; =>This Inner Loop Header: Depth=1
; ISA-NEXT:    s_or_b64 s[6:7], s[6:7], exec
; ISA-NEXT:    s_cmp_lt_u32 s0, 32
; ISA-NEXT:    s_mov_b64 s[8:9], -1
; ISA-NEXT:    s_cbranch_scc0 BB0_2
; ISA-NEXT:  ; %bb.4: ; %endif1
; ISA-NEXT:    ; in Loop: Header=BB0_3 Depth=1
; ISA-NEXT:    s_mov_b64 s[6:7], -1
; ISA-NEXT:    s_and_saveexec_b64 s[8:9], vcc
; ISA-NEXT:    s_cbranch_execz BB0_1
; ISA-NEXT:  ; %bb.5: ; %endif2
; ISA-NEXT:    ; in Loop: Header=BB0_3 Depth=1
; ISA-NEXT:    s_xor_b64 s[6:7], exec, -1
; ISA-NEXT:    s_branch BB0_1
; ISA-NEXT:  BB0_6: ; %Flow2
; ISA-NEXT:    s_or_b64 exec, exec, s[2:3]
; ISA-NEXT:    v_mov_b32_e32 v1, 0
; ISA-NEXT:    s_and_saveexec_b64 s[0:1], s[4:5]
; ISA-NEXT:  ; %bb.7: ; %if1
; ISA-NEXT:    v_sqrt_f32_e32 v1, v0
; ISA-NEXT:  ; %bb.8: ; %endloop
; ISA-NEXT:    s_or_b64 exec, exec, s[0:1]
; ISA-NEXT:    exp mrt0 v1, v1, v1, v1 done vm
; ISA-NEXT:    s_endpgm
start:
  %v0 = call float @llvm.amdgcn.interp.p1(float %1, i32 0, i32 0, i32 %0)
  br label %loop
+141 −109
Original line number Diff line number Diff line
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify %s | FileCheck -check-prefix=IR %s

; SI-LABEL: {{^}}infinite_loop:
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
; SI: [[LOOP:BB[0-9]+_[0-9]+]]:  ; %loop
; SI: s_waitcnt lgkmcnt(0)
; SI: buffer_store_dword [[REG]]
; SI: s_branch [[LOOP]]
define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loop:
; SI:       ; %bb.0: ; %entry
; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7
; SI-NEXT:  BB0_1: ; %loop
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_branch BB0_1
; IR-LABEL: @infinite_loop(
; IR-NEXT:  entry:
; IR-NEXT:    br label [[LOOP:%.*]]
; IR:       loop:
; IR-NEXT:    store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
; IR-NEXT:    br label [[LOOP]]
;
entry:
  br label %loop

@@ -16,31 +30,36 @@ loop:
  br label %loop
}


define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loop_ret:
; SI:       ; %bb.0: ; %entry
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT:    s_cbranch_execz BB1_3
; SI-NEXT:  ; %bb.1: ; %loop.preheader
; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7
; SI-NEXT:    s_and_b64 vcc, exec, -1
; SI-NEXT:  BB1_2: ; %loop
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_cbranch_vccnz BB1_2
; SI-NEXT:  BB1_3: ; %UnifiedReturnBlock
; SI-NEXT:    s_endpgm
; IR-LABEL: @infinite_loop_ret(
; IR:  br i1 %cond, label %loop, label %UnifiedReturnBlock

; IR-NEXT:  entry:
; IR-NEXT:    [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; IR-NEXT:    [[COND:%.*]] = icmp eq i32 [[TMP]], 1
; IR-NEXT:    br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
; IR:       loop:
; IR: store volatile i32 999, i32 addrspace(1)* %out, align 4
; IR: br i1 true, label %loop, label %UnifiedReturnBlock

; IR-NEXT:    store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
; IR-NEXT:    br i1 true, label [[LOOP]], label [[UNIFIEDRETURNBLOCK]]
; IR:       UnifiedReturnBlock:
; IR:  ret void


; SI-LABEL: {{^}}infinite_loop_ret:
; SI: s_cbranch_execz [[RET:BB[0-9]+_[0-9]+]]

; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
; SI: s_and_b64 vcc, exec, -1
; SI: [[LOOP:BB[0-9]+_[0-9]+]]:  ; %loop
; SI: s_waitcnt lgkmcnt(0)
; SI: buffer_store_dword [[REG]]
; SI: s_cbranch_vccnz [[LOOP]]

; SI: [[RET]]:  ; %UnifiedReturnBlock
; SI: s_endpgm
define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) {
; IR-NEXT:    ret void
;
entry:
  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
  %cond = icmp eq i32 %tmp, 1
@@ -54,44 +73,44 @@ return:
  ret void
}


define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loops:
; SI:       ; %bb.0: ; %entry
; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_cbranch_scc0 BB2_3
; SI-NEXT:  ; %bb.1: ; %loop1.preheader
; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7
; SI-NEXT:    s_and_b64 vcc, exec, -1
; SI-NEXT:  BB2_2: ; %loop1
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_cbranch_vccnz BB2_2
; SI-NEXT:    s_branch BB2_5
; SI-NEXT:  BB2_3:
; SI-NEXT:    v_mov_b32_e32 v0, 0x378
; SI-NEXT:    s_and_b64 vcc, exec, -1
; SI-NEXT:  BB2_4: ; %loop2
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_cbranch_vccnz BB2_4
; SI-NEXT:  BB2_5: ; %DummyReturnBlock
; SI-NEXT:    s_endpgm
; IR-LABEL: @infinite_loops(
; IR: br i1 undef, label %loop1, label %loop2

; IR-NEXT:  entry:
; IR-NEXT:    br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]]
; IR:       loop1:
; IR: store volatile i32 999, i32 addrspace(1)* %out, align 4
; IR: br i1 true, label %loop1, label %DummyReturnBlock

; IR-NEXT:    store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
; IR-NEXT:    br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]]
; IR:       loop2:
; IR: store volatile i32 888, i32 addrspace(1)* %out, align 4
; IR: br i1 true, label %loop2, label %DummyReturnBlock

; IR-NEXT:    store volatile i32 888, i32 addrspace(1)* [[OUT]], align 4
; IR-NEXT:    br i1 true, label [[LOOP2]], label [[DUMMYRETURNBLOCK]]
; IR:       DummyReturnBlock:
; IR: ret void


; SI-LABEL: {{^}}infinite_loops:

; SI: v_mov_b32_e32 [[REG1:v[0-9]+]], 0x3e7
; SI: s_and_b64 vcc, exec, -1

; SI: [[LOOP1:BB[0-9]+_[0-9]+]]:  ; %loop1
; SI: s_waitcnt lgkmcnt(0)
; SI: buffer_store_dword [[REG1]]
; SI: s_cbranch_vccnz [[LOOP1]]
; SI: s_branch [[RET:BB[0-9]+_[0-9]+]]

; SI: v_mov_b32_e32 [[REG2:v[0-9]+]], 0x378
; SI: s_and_b64 vcc, exec, -1

; SI: [[LOOP2:BB[0-9]+_[0-9]+]]:  ; %loop2
; SI: s_waitcnt lgkmcnt(0)
; SI: buffer_store_dword [[REG2]]
; SI: s_cbranch_vccnz [[LOOP2]]

; SI: [[RET]]:  ; %DummyReturnBlock
; SI: s_endpgm
define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
; IR-NEXT:    ret void
;
entry:
  br i1 undef, label %loop1, label %loop2

@@ -104,46 +123,59 @@ loop2:
  br label %loop2
}



define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loop_nest_ret:
; SI:       ; %bb.0: ; %entry
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT:    s_cbranch_execz BB3_5
; SI-NEXT:  ; %bb.1: ; %outer_loop.preheader
; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
; SI-NEXT:    v_cmp_ne_u32_e64 s[0:1], 3, v0
; SI-NEXT:    s_mov_b64 s[2:3], 0
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:  BB3_2: ; %outer_loop
; SI-NEXT:    ; =>This Loop Header: Depth=1
; SI-NEXT:    ; Child Loop BB3_3 Depth 2
; SI-NEXT:    s_and_b64 s[8:9], exec, vcc
; SI-NEXT:    s_or_b64 s[2:3], s[8:9], s[2:3]
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  BB3_3: ; %inner_loop
; SI-NEXT:    ; Parent Loop BB3_2 Depth=1
; SI-NEXT:    ; => This Inner Loop Header: Depth=2
; SI-NEXT:    s_and_b64 s[10:11], exec, s[0:1]
; SI-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz BB3_3
; SI-NEXT:  ; %bb.4: ; %Flow
; SI-NEXT:    ; in Loop: Header=BB3_2 Depth=1
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT:    s_cbranch_execnz BB3_2
; SI-NEXT:  BB3_5: ; %UnifiedReturnBlock
; SI-NEXT:    s_endpgm
; IR-LABEL: @infinite_loop_nest_ret(
; IR: br i1 %cond1, label %outer_loop, label %UnifiedReturnBlock

; IR-NEXT:  entry:
; IR-NEXT:    [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; IR-NEXT:    [[COND1:%.*]] = icmp eq i32 [[TMP]], 1
; IR-NEXT:    br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
; IR:       outer_loop:
; IR: br label %inner_loop

; IR-NEXT:    br label [[INNER_LOOP:%.*]]
; IR:       inner_loop:
; IR: store volatile i32 999, i32 addrspace(1)* %out, align 4
; IR: %cond3 = icmp eq i32 %tmp, 3
; IR: br i1 true, label %TransitionBlock, label %UnifiedReturnBlock

; IR-NEXT:    store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
; IR-NEXT:    [[COND3:%.*]] = icmp eq i32 [[TMP]], 3
; IR-NEXT:    br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]]
; IR:       TransitionBlock:
; IR: br i1 %cond3, label %inner_loop, label %outer_loop

; IR-NEXT:    br i1 [[COND3]], label [[INNER_LOOP]], label [[OUTER_LOOP]]
; IR:       UnifiedReturnBlock:
; IR: ret void

; SI-LABEL: {{^}}infinite_loop_nest_ret:
; SI: s_cbranch_execz [[RET:BB[0-9]+_[0-9]+]]

; SI: s_mov_b32
; SI: [[OUTER_LOOP:BB[0-9]+_[0-9]+]]:  ; %outer_loop

; SI: [[INNER_LOOP:BB[0-9]+_[0-9]+]]:  ; %inner_loop
; SI: s_waitcnt expcnt(0)
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
; SI: s_waitcnt lgkmcnt(0)
; SI: buffer_store_dword [[REG]]

; SI: s_andn2_b64 exec
; SI: s_cbranch_execnz [[INNER_LOOP]]

; SI: s_andn2_b64 exec
; SI: s_cbranch_execnz [[OUTER_LOOP]]

; SI: [[RET]]:  ; %UnifiedReturnBlock
; SI: s_endpgm
define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) {
; IR-NEXT:    ret void
;
entry:
  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
  %cond1 = icmp eq i32 %tmp, 1
+409 −196

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; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s

; FUNC-LABEL: {{^}}break_inserted_outside_of_loop:

; SI: [[LOOP_LABEL:[A-Z0-9]+]]:
; Lowered break instructin:
; SI: s_or_b64
; Lowered Loop instruction:
; SI: s_andn2_b64
; s_cbranch_execnz [[LOOP_LABEL]]
; SI: s_endpgm
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=FLAT %s

define amdgpu_kernel void @break_inserted_outside_of_loop(i32 addrspace(1)* %out, i32 %a) {
; SI-LABEL: break_inserted_outside_of_loop:
; SI:       ; %bb.0: ; %main_body
; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT:    s_load_dword s0, s[0:1], 0xb
; SI-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, -1, 0
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_and_b32_e32 v0, s0, v0
; SI-NEXT:    v_and_b32_e32 v0, 1, v0
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
; SI-NEXT:    s_mov_b64 s[0:1], 0
; SI-NEXT:  BB0_1: ; %ENDIF
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    s_and_b64 s[2:3], exec, vcc
; SI-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
; SI-NEXT:    s_andn2_b64 exec, exec, s[0:1]
; SI-NEXT:    s_cbranch_execnz BB0_1
; SI-NEXT:  ; %bb.2: ; %ENDLOOP
; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    v_mov_b32_e32 v0, 0
; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT:    s_endpgm
;
; FLAT-LABEL: break_inserted_outside_of_loop:
; FLAT:       ; %bb.0: ; %main_body
; FLAT-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
; FLAT-NEXT:    s_load_dword s0, s[0:1], 0x2c
; FLAT-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
; FLAT-NEXT:    v_and_b32_e32 v0, s0, v0
; FLAT-NEXT:    v_and_b32_e32 v0, 1, v0
; FLAT-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
; FLAT-NEXT:    s_mov_b64 s[0:1], 0
; FLAT-NEXT:  BB0_1: ; %ENDIF
; FLAT-NEXT:    ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT:    s_and_b64 s[2:3], exec, vcc
; FLAT-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
; FLAT-NEXT:    s_andn2_b64 exec, exec, s[0:1]
; FLAT-NEXT:    s_cbranch_execnz BB0_1
; FLAT-NEXT:  ; %bb.2: ; %ENDLOOP
; FLAT-NEXT:    s_or_b64 exec, exec, s[0:1]
; FLAT-NEXT:    s_mov_b32 s7, 0xf000
; FLAT-NEXT:    s_mov_b32 s6, -1
; FLAT-NEXT:    v_mov_b32_e32 v0, 0
; FLAT-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; FLAT-NEXT:    s_endpgm
main_body:
  %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
  %0 = and i32 %a, %tid
@@ -25,25 +64,54 @@ ENDIF:
  br i1 %1, label %ENDLOOP, label %ENDIF
}


; FUNC-LABEL: {{^}}phi_cond_outside_loop:

; SI:     s_mov_b64         [[LEFT:s\[[0-9]+:[0-9]+\]]], 0
; SI:     s_mov_b64         [[PHI:s\[[0-9]+:[0-9]+\]]], 0

; SI: ; %else
; SI:     v_cmp_eq_u32_e64  [[TMP:s\[[0-9]+:[0-9]+\]]],

; SI: ; %endif

; SI: [[LOOP_LABEL:BB[0-9]+_[0-9]+]]: ; %loop
; SI:     s_and_b64         [[TMP1:s\[[0-9]+:[0-9]+\]]], exec, [[PHI]]
; SI:     s_or_b64          [[LEFT]], [[TMP1]], [[LEFT]]
; SI:     s_andn2_b64       exec, exec, [[LEFT]]
; SI:     s_cbranch_execnz  [[LOOP_LABEL]]
; SI:     s_endpgm

define amdgpu_kernel void @phi_cond_outside_loop(i32 %b) {
; SI-LABEL: phi_cond_outside_loop:
; SI:       ; %bb.0: ; %entry
; SI-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, -1, 0
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT:    s_mov_b64 s[2:3], 0
; SI-NEXT:    s_mov_b64 s[4:5], 0
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz BB1_2
; SI-NEXT:  ; %bb.1: ; %else
; SI-NEXT:    s_load_dword s0, s[0:1], 0x9
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s0, 0
; SI-NEXT:    s_and_b64 s[4:5], s[0:1], exec
; SI-NEXT:  BB1_2: ; %endif
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:  BB1_3: ; %loop
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    s_and_b64 s[0:1], exec, s[4:5]
; SI-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
; SI-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT:    s_cbranch_execnz BB1_3
; SI-NEXT:  ; %bb.4: ; %exit
; SI-NEXT:    s_endpgm
;
; FLAT-LABEL: phi_cond_outside_loop:
; FLAT:       ; %bb.0: ; %entry
; FLAT-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
; FLAT-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; FLAT-NEXT:    s_mov_b64 s[2:3], 0
; FLAT-NEXT:    s_mov_b64 s[4:5], 0
; FLAT-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; FLAT-NEXT:    s_cbranch_execz BB1_2
; FLAT-NEXT:  ; %bb.1: ; %else
; FLAT-NEXT:    s_load_dword s0, s[0:1], 0x24
; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
; FLAT-NEXT:    v_cmp_eq_u32_e64 s[0:1], s0, 0
; FLAT-NEXT:    s_and_b64 s[4:5], s[0:1], exec
; FLAT-NEXT:  BB1_2: ; %endif
; FLAT-NEXT:    s_or_b64 exec, exec, s[6:7]
; FLAT-NEXT:  BB1_3: ; %loop
; FLAT-NEXT:    ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT:    s_and_b64 s[0:1], exec, s[4:5]
; FLAT-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
; FLAT-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; FLAT-NEXT:    s_cbranch_execnz BB1_3
; FLAT-NEXT:  ; %bb.4: ; %exit
; FLAT-NEXT:    s_endpgm
entry:
  %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
  %0 = icmp eq i32 %tid , 0
@@ -67,11 +135,12 @@ exit:
  ret void
}

; FIXME: should emit s_endpgm
; CHECK-LABEL: {{^}}switch_unreachable:
; CHECK-NOT: s_endpgm
; CHECK: .Lfunc_end2
define amdgpu_kernel void @switch_unreachable(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {
; SI-LABEL: switch_unreachable:
; SI:       ; %bb.0: ; %centry
;
; FLAT-LABEL: switch_unreachable:
; FLAT:       ; %bb.0: ; %centry
centry:
  switch i32 %x, label %sw.default [
    i32 0, label %sw.bb
@@ -90,29 +159,99 @@ sw.epilog:

declare float @llvm.fabs.f32(float) nounwind readnone

; This broke the old AMDIL cfg structurizer
; FUNC-LABEL: {{^}}loop_land_info_assert:
; SI:      v_cmp_lt_i32_e64 [[CMP4:s\[[0-9:]+\]]], s{{[0-9]+}}, 4{{$}}
; SI:      s_and_b64        [[CMP4M:s\[[0-9]+:[0-9]+\]]], exec, [[CMP4]]

; SI: [[WHILELOOP:BB[0-9]+_[0-9]+]]: ; %while.cond
; SI:      s_cbranch_vccz [[FOR_COND_PH:BB[0-9]+_[0-9]+]]

; SI:      [[CONVEX_EXIT:BB[0-9_]+]]
; SI:      s_mov_b64        vcc,
; SI-NEXT: s_cbranch_vccnz  [[ENDPGM:BB[0-9]+_[0-9]+]]

; SI:      s_cbranch_vccnz  [[WHILELOOP]]

; SI: ; %if.else
; SI:      buffer_store_dword

; SI: [[FOR_COND_PH]]: ; %for.cond.preheader
; SI:      s_cbranch_vccz [[ENDPGM]]

; SI:      [[ENDPGM]]:
; SI-NEXT: s_endpgm
define amdgpu_kernel void @loop_land_info_assert(i32 %c0, i32 %c1, i32 %c2, i32 %c3, i32 %x, i32 %y, i1 %arg) nounwind {
; SI-LABEL: loop_land_info_assert:
; SI:       ; %bb.0: ; %entry
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x9
; SI-NEXT:    s_load_dword s4, s[0:1], 0xc
; SI-NEXT:    s_brev_b32 s5, 44
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s2, 0
; SI-NEXT:    v_cmp_lt_i32_e64 s[2:3], s3, 4
; SI-NEXT:    s_or_b64 s[8:9], s[0:1], s[2:3]
; SI-NEXT:    s_and_b64 s[0:1], exec, s[2:3]
; SI-NEXT:    s_and_b64 s[2:3], exec, s[8:9]
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_cmp_lt_f32_e64 s[8:9], |v0|, s5
; SI-NEXT:    v_mov_b32_e32 v0, 3
; SI-NEXT:  BB3_1: ; %while.cond
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    s_mov_b64 vcc, s[0:1]
; SI-NEXT:    s_cbranch_vccz BB3_5
; SI-NEXT:  ; %bb.2: ; %convex.exit
; SI-NEXT:    ; in Loop: Header=BB3_1 Depth=1
; SI-NEXT:    s_mov_b64 vcc, s[2:3]
; SI-NEXT:    s_cbranch_vccnz BB3_8
; SI-NEXT:  ; %bb.3: ; %if.end
; SI-NEXT:    ; in Loop: Header=BB3_1 Depth=1
; SI-NEXT:    s_andn2_b64 vcc, exec, s[8:9]
; SI-NEXT:    s_cbranch_vccnz BB3_1
; SI-NEXT:  ; %bb.4: ; %if.else
; SI-NEXT:    ; in Loop: Header=BB3_1 Depth=1
; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT:    s_branch BB3_1
; SI-NEXT:  BB3_5: ; %for.cond.preheader
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, 0x3e8
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, s4, v0
; SI-NEXT:    s_and_b64 vcc, exec, vcc
; SI-NEXT:    s_cbranch_vccz BB3_8
; SI-NEXT:  ; %bb.6: ; %for.body
; SI-NEXT:    s_and_b64 vcc, exec, -1
; SI-NEXT:  BB3_7: ; %self.loop
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    s_cbranch_vccnz BB3_7
; SI-NEXT:  BB3_8: ; %DummyReturnBlock
; SI-NEXT:    s_endpgm
;
; FLAT-LABEL: loop_land_info_assert:
; FLAT:       ; %bb.0: ; %entry
; FLAT-NEXT:    s_mov_b32 s7, 0xf000
; FLAT-NEXT:    s_mov_b32 s6, -1
; FLAT-NEXT:    buffer_load_dword v0, off, s[4:7], 0
; FLAT-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
; FLAT-NEXT:    s_load_dword s4, s[0:1], 0x30
; FLAT-NEXT:    s_brev_b32 s5, 44
; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
; FLAT-NEXT:    v_cmp_gt_i32_e64 s[0:1], s2, 0
; FLAT-NEXT:    v_cmp_lt_i32_e64 s[2:3], s3, 4
; FLAT-NEXT:    s_or_b64 s[8:9], s[0:1], s[2:3]
; FLAT-NEXT:    s_and_b64 s[0:1], exec, s[2:3]
; FLAT-NEXT:    s_and_b64 s[2:3], exec, s[8:9]
; FLAT-NEXT:    s_waitcnt vmcnt(0)
; FLAT-NEXT:    v_cmp_lt_f32_e64 s[8:9], |v0|, s5
; FLAT-NEXT:    v_mov_b32_e32 v0, 3
; FLAT-NEXT:  BB3_1: ; %while.cond
; FLAT-NEXT:    ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT:    s_mov_b64 vcc, s[0:1]
; FLAT-NEXT:    s_cbranch_vccz BB3_5
; FLAT-NEXT:  ; %bb.2: ; %convex.exit
; FLAT-NEXT:    ; in Loop: Header=BB3_1 Depth=1
; FLAT-NEXT:    s_mov_b64 vcc, s[2:3]
; FLAT-NEXT:    s_cbranch_vccnz BB3_8
; FLAT-NEXT:  ; %bb.3: ; %if.end
; FLAT-NEXT:    ; in Loop: Header=BB3_1 Depth=1
; FLAT-NEXT:    s_andn2_b64 vcc, exec, s[8:9]
; FLAT-NEXT:    s_cbranch_vccnz BB3_1
; FLAT-NEXT:  ; %bb.4: ; %if.else
; FLAT-NEXT:    ; in Loop: Header=BB3_1 Depth=1
; FLAT-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; FLAT-NEXT:    s_branch BB3_1
; FLAT-NEXT:  BB3_5: ; %for.cond.preheader
; FLAT-NEXT:    v_mov_b32_e32 v0, 0x3e8
; FLAT-NEXT:    v_cmp_lt_i32_e32 vcc, s4, v0
; FLAT-NEXT:    s_and_b64 vcc, exec, vcc
; FLAT-NEXT:    s_cbranch_vccz BB3_8
; FLAT-NEXT:  ; %bb.6: ; %for.body
; FLAT-NEXT:    s_and_b64 vcc, exec, -1
; FLAT-NEXT:  BB3_7: ; %self.loop
; FLAT-NEXT:    ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT:    s_cbranch_vccnz BB3_7
; FLAT-NEXT:  BB3_8: ; %DummyReturnBlock
; FLAT-NEXT:    s_endpgm
entry:
  %cmp = icmp sgt i32 %c0, 0
  br label %while.cond.outer
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