Commit 533471ff authored by Simon Atanasyan's avatar Simon Atanasyan
Browse files

[MIPS] Remove unused tblgen template args. NFC 

Identified in D109359.
parent 3b9470a6

llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td

+1 −1
Original line number Diff line number Diff line
@@ -958,7 +958,7 @@ class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct> 
  let Inst{5-0}   = 0b111100;

}



class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {

class CMP_BRANCH_OFF21_FM_MMR6<bits<6> funct> : MipsR6Inst {

  bits<5> rs;

  bits<21> offset;

llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

+14 −16
Original line number Diff line number Diff line
@@ -62,8 +62,8 @@ class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>; 
class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;

class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;

class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;

class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;

class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;

class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<0b100000>;

class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<0b101000>;

class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,

                      DecodeDisambiguates<"POP75GroupBranchMMR6">;

class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
@@ -406,7 +406,7 @@ class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>; 
class BRK_MMR6_DESC : BRK_FT<"break">;



class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,

                           RegisterOperand GPROpnd, InstrItinClass Itin>

                           InstrItinClass Itin>

      : MMR6Arch<instr_asm> {

  dag OutOperandList = (outs);

  dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
@@ -416,10 +416,8 @@ class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd, 
  InstrItinClass Itinerary = Itin;

}



class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,

                                             II_CACHE>;

class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,

                                             II_PREF>;

class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, II_CACHE>;

class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, II_PREF>;



class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,

                            RegisterOperand GPROpnd, InstrItinClass Itin>
@@ -1197,21 +1195,21 @@ class SWM16_MMR6_DESC 
  ComplexPattern Addr = addr;

}



class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,

                          SDPatternOperator OpNode, InstrItinClass Itin,

                          Operand MemOpnd>

class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd,

                          InstrItinClass Itin, Operand MemOpnd>

    : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),

                      !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,

      MMR6Arch<opstr> {

  let DecoderMethod = "DecodeMemMMImm4";

  let mayStore = 1;

}

class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,

                                           truncstorei8, II_SB, mem_mm_4>;

class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,

                                           truncstorei16, II_SH, mem_mm_4_lsl1>;

class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,

                                           store, II_SW, mem_mm_4_lsl2>;



class SB16_MMR6_DESC

    : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>;

class SH16_MMR6_DESC

    : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>;

class SW16_MMR6_DESC

    : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>;



class SWSP_MMR6_DESC

    : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),

llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td

+31 −42
Original line number Diff line number Diff line
@@ -281,56 +281,45 @@ class SHRLV_PH_MMR2_DESC : SHLLV_R3_MM_DESC_BASE< 
class SHRLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE<

  "shrlv.qb", int_mips_shrl_qb, NoItinerary, DSPROpnd>;



class EXT_MM_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,

                          InstrItinClass itin> {

class EXT_MM_2R_DESC_BASE<string instr_asm> {

  dag OutOperandList = (outs GPR32Opnd:$rt);

  dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$rs);

  string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $rs");

  InstrItinClass Itinerary = itin;

  InstrItinClass Itinerary = NoItinerary;

}

class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,

                          InstrItinClass itin> {

class EXT_MM_1R_DESC_BASE<string instr_asm> {

  dag OutOperandList = (outs GPR32Opnd:$rt);

  dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$imm);

  string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $imm");

  InstrItinClass Itinerary = itin;

  InstrItinClass Itinerary = NoItinerary;

}



class EXTP_MM_DESC

    : EXT_MM_1R_DESC_BASE<"extp", MipsEXTP, NoItinerary>,

      Uses<[DSPPos]>, Defs<[DSPEFI]>;

class EXTPDP_MM_DESC

    : EXT_MM_1R_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,

      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;

class EXTPDPV_MM_DESC

    : EXT_MM_2R_DESC_BASE<"extpdpv", MipsEXTPDP, NoItinerary>,

      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;

class EXTPV_MM_DESC

    : EXT_MM_2R_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,

      Uses<[DSPPos]>, Defs<[DSPEFI]>;

class EXTR_W_MM_DESC

    : EXT_MM_1R_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,

      Defs<[DSPOutFlag23]>;

class EXTR_R_W_MM_DESC

    : EXT_MM_1R_DESC_BASE<"extr_r.w", MipsEXTR_R_W, NoItinerary>,

class EXTP_MM_DESC : EXT_MM_1R_DESC_BASE<"extp">,

                     Uses<[DSPPos]>,

                     Defs<[DSPEFI]>;

class EXTPDP_MM_DESC : EXT_MM_1R_DESC_BASE<"extpdp">,

                       Uses<[DSPPos]>,

                       Defs<[DSPPos, DSPEFI]>;

class EXTPDPV_MM_DESC : EXT_MM_2R_DESC_BASE<"extpdpv">,

                        Uses<[DSPPos]>,

                        Defs<[DSPPos, DSPEFI]>;

class EXTPV_MM_DESC : EXT_MM_2R_DESC_BASE<"extpv">,

                      Uses<[DSPPos]>,

                      Defs<[DSPEFI]>;

class EXTR_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr.w">,

                       Defs<[DSPOutFlag23]>;

class EXTR_RS_W_MM_DESC

    : EXT_MM_1R_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, NoItinerary>,

class EXTR_R_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_r.w">,

                         Defs<[DSPOutFlag23]>;

class EXTR_S_H_MM_DESC

    : EXT_MM_1R_DESC_BASE<"extr_s.h", MipsEXTR_S_H, NoItinerary>,

class EXTR_RS_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_rs.w">,

                          Defs<[DSPOutFlag23]>;

class EXTRV_W_MM_DESC

    : EXT_MM_2R_DESC_BASE<"extrv.w", MipsEXTR_W, NoItinerary>,

class EXTR_S_H_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_s.h">,

                         Defs<[DSPOutFlag23]>;

class EXTRV_R_W_MM_DESC

    : EXT_MM_2R_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, NoItinerary>,

class EXTRV_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv.w">, Defs<[DSPOutFlag23]>;

class EXTRV_R_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_r.w">,

                          Defs<[DSPOutFlag23]>;

class EXTRV_RS_W_MM_DESC

    : EXT_MM_2R_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, NoItinerary>,

class EXTRV_RS_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_rs.w">,

                           Defs<[DSPOutFlag23]>;

class EXTRV_S_H_MM_DESC

    : EXT_MM_2R_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, NoItinerary>,

class EXTRV_S_H_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_s.h">,

                          Defs<[DSPOutFlag23]>;



class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,

llvm/lib/Target/Mips/MicroMipsInstrInfo.td

+26 −35
Original line number Diff line number Diff line
@@ -195,8 +195,7 @@ def simm23_lsl2 : Operand<i32> { 
  let DecoderMethod = "DecodeSimm23Lsl2";

}



class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,

                      RegisterOperand RO> :

class CompactBranchMM<string opstr, DAGOperand opnd, RegisterOperand RO> :

  InstSE<(outs), (ins RO:$rs, opnd:$offset),

         !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {

  let isBranch = 1;
@@ -240,7 +239,7 @@ MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt), 
  let DecoderMethod = "DecodeMovePOperands";

}



class StorePairMM<string opstr, ComplexPattern Addr = addr>

class StorePairMM<string opstr>

    :  InstSE<(outs), (ins GPR32Opnd:$rt, GPR32Opnd:$rt2, mem_simm12:$addr),

         !strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {

  let DecoderMethod = "DecodeMemMMImm12";
@@ -248,7 +247,7 @@ class StorePairMM<string opstr, ComplexPattern Addr = addr> 
  let AsmMatchConverter = "ConvertXWPOperands";

}



class LoadPairMM<string opstr, ComplexPattern Addr = addr>

class LoadPairMM<string opstr>

    : InstSE<(outs GPR32Opnd:$rt, GPR32Opnd:$rt2), (ins mem_simm12:$addr),

          !strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {

  let DecoderMethod = "DecodeMemMMImm12";
@@ -332,7 +331,7 @@ class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO, 
  MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),

                  !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;



class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,

class LoadMM16<string opstr, DAGOperand RO,

               InstrItinClass Itin, Operand MemOpnd> :

  MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),

                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
@@ -341,8 +340,7 @@ class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode, 
  let mayLoad = 1;

}



class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,

                SDPatternOperator OpNode, InstrItinClass Itin,

class StoreMM16<string opstr, DAGOperand RTOpnd, InstrItinClass Itin,

                Operand MemOpnd> :

  MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),

                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
@@ -499,8 +497,7 @@ let isCall = 1, hasDelaySlot = 1, Defs = [RA] in { 
           !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;

}



class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,

                              SDPatternOperator OpNode = null_frag> :

class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO> :

  InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),

         !strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;
@@ -540,34 +537,28 @@ def reglist16 : Operand<i32> { 
  let ParserMatchClass = RegList16AsmOperand;

}



class StoreMultMM<string opstr,

            InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :

class StoreMultMM<string opstr, InstrItinClass Itin> :

  InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),

         !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {

  let DecoderMethod = "DecodeMemMMImm12";

  let mayStore = 1;

}



class LoadMultMM<string opstr,

            InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :

class LoadMultMM<string opstr, InstrItinClass Itin> :

  InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),

          !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {

  let DecoderMethod = "DecodeMemMMImm12";

  let mayLoad = 1;

}



class StoreMultMM16<string opstr,

                    InstrItinClass Itin = NoItinerary,

                    ComplexPattern Addr = addr> :

class StoreMultMM16<string opstr, InstrItinClass Itin> :

  MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),

                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {

  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";

  let mayStore = 1;

}



class LoadMultMM16<string opstr,

                   InstrItinClass Itin = NoItinerary,

                   ComplexPattern Addr = addr> :

class LoadMultMM16<string opstr, InstrItinClass Itin> :

  MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),

                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {

  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
@@ -636,20 +627,20 @@ let FastISelShouldIgnore = 1 in { 
  def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,

                 LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;

}

def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,

                        mem_mm_4>, LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;

def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,

                        mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;

def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,

def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, II_LBU, mem_mm_4>,

               LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;

def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, II_LHU, mem_mm_4_lsl1>,

               LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;

def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, II_LW, mem_mm_4_lsl2>,

                      LOAD_STORE_FM_MM16<0x1a>, ISA_MICROMIPS;

def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,

                        II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>,

def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>,

              LOAD_STORE_FM_MM16<0x22>,

              ISA_MICROMIPS32_NOT_MIPS32R6;

def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>,

              LOAD_STORE_FM_MM16<0x2a>,

              ISA_MICROMIPS32_NOT_MIPS32R6;

def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,

                        II_SH, mem_mm_4_lsl1>,

                        LOAD_STORE_FM_MM16<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6;

def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,

                        mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>,

def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>,

              LOAD_STORE_FM_MM16<0x3a>,

              ISA_MICROMIPS32_NOT_MIPS32R6;

def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,

                         LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
@@ -713,9 +704,9 @@ let DecoderNamespace = "MicroMips" in { 
                POOL32A_CFTC2_FM_MM<0b1101110100>, ISA_MICROMIPS;



  /// Compact Branch Instructions

  def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,

  def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, GPR32Opnd>,

                 COMPACT_BRANCH_FM_MM<0x7>, ISA_MICROMIPS32_NOT_MIPS32R6;

  def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,

  def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, GPR32Opnd>,

                 COMPACT_BRANCH_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;



  /// Arithmetic Instructions (ALU Immediate)

llvm/lib/Target/Mips/Mips16InstrInfo.td

+6 −6
Original line number Diff line number Diff line
@@ -304,14 +304,14 @@ class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 
//

// MULT

//

class FMULT16_ins<string asmstr, InstrItinClass itin> :

class FMULT16_ins<string asmstr> :

  MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),

               !strconcat(asmstr, "\t$rx, $ry"), []>;



//

// MULT-LO

//

class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :

class FMULT16_LO_ins<string asmstr> :

  MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),

               !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {

  let isCodeGenOnly=1;
@@ -895,13 +895,13 @@ def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> { 
//

// Pseudo Instruction for mult

//

def MultRxRy16:  FMULT16_ins<"mult",  IIM16Alu> {

def MultRxRy16:  FMULT16_ins<"mult"> {

  let isCommutable = 1;

  let hasSideEffects = 0;

  let Defs = [HI0, LO0];

}



def MultuRxRy16: FMULT16_ins<"multu", IIM16Alu> {

def MultuRxRy16: FMULT16_ins<"multu"> {

  let isCommutable = 1;

  let hasSideEffects = 0;

  let Defs = [HI0, LO0];
@@ -912,7 +912,7 @@ def MultuRxRy16: FMULT16_ins<"multu", IIM16Alu> { 
// Purpose: Multiply Word

// To multiply 32-bit signed integers.

//

def MultRxRyRz16: FMULT16_LO_ins<"mult", IIM16Alu> {

def MultRxRyRz16: FMULT16_LO_ins<"mult"> {

  let isCommutable = 1;

  let hasSideEffects = 0;

  let Defs = [HI0, LO0];
@@ -923,7 +923,7 @@ def MultRxRyRz16: FMULT16_LO_ins<"mult", IIM16Alu> { 
// Purpose: Multiply Unsigned Word

// To multiply 32-bit unsigned integers.

//

def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIM16Alu> {

def MultuRxRyRz16: FMULT16_LO_ins<"multu"> {

  let isCommutable = 1;

  let hasSideEffects = 0;

  let Defs = [HI0, LO0];