Commit 5165b2b5 authored by Tim Northover's avatar Tim Northover
Browse files

AArch64+ARM: make LLVM consider system registers volatile. 

Some of the system registers readable on AArch64 and ARM platforms
return different values with each read (for example a timer counter),
these shouldn't be hoisted outside loops or otherwise interfered with,
but the normal @llvm.read_register intrinsic is only considered to read
memory.

This introduces a separate @llvm.read_volatile_register intrinsic and
maps all system-registers on ARM platforms to use it for the
__builtin_arm_rsr calls. Registers declared with asm("r9") or similar
are unaffected.
parent fe591224

clang/lib/CodeGen/CGBuiltin.cpp

+29 −13
Original line number Diff line number Diff line
@@ -6361,6 +6361,12 @@ Value *CodeGenFunction::GetValueForARMHint(unsigned BuiltinID) { 
                            llvm::ConstantInt::get(Int32Ty, Value));

}













enum SpecialRegisterAccessKind {













  NormalRead,













  VolatileRead,













  Write,













};



























// Generates the IR for the read/write special register builtin,















// ValueType is the type of the value that is to be written or read,















// RegisterType is the type of the register being written to or read from.









@@ -6368,7 +6374,7 @@ static Value *EmitSpecialRegisterBuiltin(CodeGenFunction &CGF,













                                         const CallExpr *E,















                                         llvm::Type *RegisterType,















                                         llvm::Type *ValueType,













                                         bool IsRead,













                                         SpecialRegisterAccessKind AccessKind,















                                         StringRef SysReg = "") {















  // write and register intrinsics only support 32 and 64 bit operations.















  assert((RegisterType->isIntegerTy(32) || RegisterType->isIntegerTy(64))









@@ -6393,8 +6399,12 @@ static Value *EmitSpecialRegisterBuiltin(CodeGenFunction &CGF,













  assert(!(RegisterType->isIntegerTy(32) && ValueType->isIntegerTy(64))















            && "Can't fit 64-bit value in 32-bit register");



























  if (IsRead) {













    llvm::Function *F = CGM.getIntrinsic(llvm::Intrinsic::read_register, Types);













  if (AccessKind != Write) {













    assert(AccesKind == NormalRead || AccessKind == VolatileRead);













    llvm::Function *F = CGM.getIntrinsic(













        AccessKind == VolatileRead ? llvm::Intrinsic::read_volatile_register













                                   : llvm::Intrinsic::read_register,













        Types);















    llvm::Value *Call = Builder.CreateCall(F, Metadata);





























    if (MixedTypes)










@@ -6773,9 +6783,11 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,













      BuiltinID == ARM::BI__builtin_arm_wsr64 ||















      BuiltinID == ARM::BI__builtin_arm_wsrp) {



























    bool IsRead = BuiltinID == ARM::BI__builtin_arm_rsr ||













    SpecialRegisterAccessKind AccessKind = Write;













    if (BuiltinID == ARM::BI__builtin_arm_rsr ||















        BuiltinID == ARM::BI__builtin_arm_rsr64 ||













                  BuiltinID == ARM::BI__builtin_arm_rsrp;













        BuiltinID == ARM::BI__builtin_arm_rsrp)













      AccessKind = VolatileRead;





























    bool IsPointerBuiltin = BuiltinID == ARM::BI__builtin_arm_rsrp ||















                            BuiltinID == ARM::BI__builtin_arm_wsrp;









@@ -6794,7 +6806,8 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,













      ValueType = RegisterType = Int32Ty;















    }



























    return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead);













    return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType,













                                      AccessKind);















  }





























  // Deal with MVE builtins










@@ -8834,9 +8847,11 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,













      BuiltinID == AArch64::BI__builtin_arm_wsr64 ||















      BuiltinID == AArch64::BI__builtin_arm_wsrp) {



























    bool IsRead = BuiltinID == AArch64::BI__builtin_arm_rsr ||













    SpecialRegisterAccessKind AccessKind = Write;













    if (BuiltinID == AArch64::BI__builtin_arm_rsr ||















        BuiltinID == AArch64::BI__builtin_arm_rsr64 ||













                  BuiltinID == AArch64::BI__builtin_arm_rsrp;













        BuiltinID == AArch64::BI__builtin_arm_rsrp)













      AccessKind = VolatileRead;





























    bool IsPointerBuiltin = BuiltinID == AArch64::BI__builtin_arm_rsrp ||















                            BuiltinID == AArch64::BI__builtin_arm_wsrp;









@@ -8854,7 +8869,8 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,













      ValueType = Int32Ty;















    }



























    return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead);













    return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType,













                                      AccessKind);















  }





























  if (BuiltinID == AArch64::BI_ReadStatusReg ||










@@ -14797,7 +14813,7 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,













  }















  case AMDGPU::BI__builtin_amdgcn_read_exec: {















    CallInst *CI = cast<CallInst>(













      EmitSpecialRegisterBuiltin(*this, E, Int64Ty, Int64Ty, true, "exec"));













      EmitSpecialRegisterBuiltin(*this, E, Int64Ty, Int64Ty, NormalRead, "exec"));















    CI->setConvergent();















    return CI;















  }









@@ -14806,7 +14822,7 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,













    StringRef RegName = BuiltinID == AMDGPU::BI__builtin_amdgcn_read_exec_lo ?















      "exec_lo" : "exec_hi";















    CallInst *CI = cast<CallInst>(













      EmitSpecialRegisterBuiltin(*this, E, Int32Ty, Int32Ty, true, RegName));













      EmitSpecialRegisterBuiltin(*this, E, Int32Ty, Int32Ty, NormalRead, RegName));















    CI->setConvergent();















    return CI;















  }

























clang/test/CodeGen/builtins-arm.c



+3
−3






























Original line number
Diff line number
Diff line








@@ -222,19 +222,19 @@ uint64_t mrrc2() {













}































unsigned rsr() {













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M0:.*]])













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_volatile_register.i32(metadata ![[M0:.*]])















  // CHECK-NEXT: ret i32 [[V0]]















  return __builtin_arm_rsr("cp1:2:c3:c4:5");















}































unsigned long long rsr64() {













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata ![[M1:.*]])













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M1:.*]])















  // CHECK-NEXT: ret i64 [[V0]]















  return __builtin_arm_rsr64("cp1:2:c3");















}































void *rsrp() {













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M2:.*]])













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_volatile_register.i32(metadata ![[M2:.*]])















  // CHECK-NEXT: [[V1:[%A-Za-z0-9.]+]] = inttoptr i32 [[V0]] to i8*















  // CHECK-NEXT: ret i8* [[V1]]















  return __builtin_arm_rsrp("sysreg");

































clang/test/CodeGen/builtins-arm64.c



+3
−3






























Original line number
Diff line number
Diff line








@@ -68,7 +68,7 @@ int32_t jcvt(double v) {













__typeof__(__builtin_arm_rsr("1:2:3:4:5")) rsr(void);































uint32_t rsr() {













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])















  // CHECK-NEXT: trunc i64 [[V0]] to i32















  return __builtin_arm_rsr("1:2:3:4:5");















}









@@ -76,12 +76,12 @@ uint32_t rsr() {













__typeof__(__builtin_arm_rsr64("1:2:3:4:5")) rsr64(void);































uint64_t rsr64(void) {













  // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])













  // CHECK: call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])















  return __builtin_arm_rsr64("1:2:3:4:5");















}































void *rsrp() {













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])













  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])















  // CHECK-NEXT: inttoptr i64 [[V0]] to i8*















  return __builtin_arm_rsrp("1:2:3:4:5");















}

































llvm/docs/LangRef.rst



+16
−8






























Original line number
Diff line number
Diff line








@@ -11643,9 +11643,11 @@ the escaped allocas are allocated, which would break attempts to use













'``llvm.localrecover``'.





























.. _int_read_register:













.. _int_read_volatile_register:















.. _int_write_register:



























'``llvm.read_register``' and '``llvm.write_register``' Intrinsics













'``llvm.read_register``', '``llvm.read_volatile_register``', and













'``llvm.write_register``' Intrinsics















^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^





























Syntax:









@@ -11655,6 +11657,8 @@ Syntax:



























      declare i32 @llvm.read_register.i32(metadata)















      declare i64 @llvm.read_register.i64(metadata)













      declare i32 @llvm.read_volatile_register.i32(metadata)













      declare i64 @llvm.read_volatile_register.i64(metadata)















      declare void @llvm.write_register.i32(metadata, i32 @value)















      declare void @llvm.write_register.i64(metadata, i64 @value)















      !0 = !{!"sp\00"}









@@ -11662,17 +11666,21 @@ Syntax:













Overview:















"""""""""



























The '``llvm.read_register``' and '``llvm.write_register``' intrinsics













provides access to the named register. The register must be valid on













the architecture being compiled to. The type needs to be compatible













with the register being read.













The '``llvm.read_register``', '``llvm.read_volatile_register``', and













'``llvm.write_register``' intrinsics provide access to the named register.













The register must be valid on the architecture being compiled to. The type













needs to be compatible with the register being read.





























Semantics:















""""""""""



























The '``llvm.read_register``' intrinsic returns the current value of the













register, where possible. The '``llvm.write_register``' intrinsic sets













the current value of the register, where possible.













The '``llvm.read_register``' and '``llvm.read_volatile_register``' intrinsics













return the current value of the register, where possible. The













'``llvm.write_register``' intrinsic sets the current value of the register,













where possible.

























A call to '``llvm.read_volatile_register``' is assumed to have side-effects













and possibly return a different value each time (e.g. for a timer register).





























This is useful to implement named register global variables that need















to always be mapped to a specific register, as is common practice on

































llvm/include/llvm/IR/Intrinsics.td



+3
−0






























Original line number
Diff line number
Diff line








@@ -458,6 +458,9 @@ def int_read_register  : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty],













                                   [IntrReadMem], "llvm.read_register">;















def int_write_register : Intrinsic<[], [llvm_metadata_ty, llvm_anyint_ty],















                                   [], "llvm.write_register">;













def int_read_volatile_register  : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty],













                                            [IntrHasSideEffects],













                                             "llvm.read_volatile_register">;































// Gets the address of the local variable area. This is typically a copy of the















// stack, frame, or base pointer depending on the type of prologue.