Commit 510792a2 authored by Mark Murray's avatar Mark Murray
Browse files

[ARM][MVE][Intrinsics] Add VMINQ/VMAXQ/VMINNMQ/VMAXNMQ intrinsics. 

Summary: Add VMINQ/VMAXQ/VMINNMQ/VMAXNMQ intrinsics and their predicated versions. Add unit tests.

Subscribers: kristof.beyls, hiraditya, dmgreen, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D70829
parent 8ab3b4de

clang/include/clang/Basic/arm_mve.td

+42 −0
Original line number Diff line number Diff line
@@ -105,6 +105,26 @@ defm vornq_m: predicated_bit_op_fp<"orn_predicated">; 
defm vorrq_m: predicated_bit_op_fp<"orr_predicated">;

}



// Predicated intrinsics - Int types only

let params = T.Int in {

def vminq_m: Intrinsic<

    Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),

    (IRInt<"min_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;

def vmaxq_m: Intrinsic<

    Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),

    (IRInt<"max_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;

}



// Predicated intrinsics - Float types only

let params = T.Float in {

def vminnmq_m: Intrinsic<

    Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),

    (IRInt<"min_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;

def vmaxnmq_m: Intrinsic<

    Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),

    (IRInt<"max_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;

}



let params = T.Int in {

def vminvq: Intrinsic<Scalar, (args Scalar:$prev, Vector:$vec),

    (Scalar (IRInt<"minv", [Vector], 1> $prev, $vec))>;
@@ -173,6 +193,28 @@ let params = T.Float in { 
  defm: compare<"le", fcmp_le>;

}



let params = T.Signed in {

  def vminq: Intrinsic<Vector, (args Vector:$a, Vector:$b),

                               (select (icmp_sle $a, $b), $a, $b)>;

  def vmaxq: Intrinsic<Vector, (args Vector:$a, Vector:$b),

                               (select (icmp_sge $a, $b), $a, $b)>;

}

let params = T.Unsigned in {

  def vminqu: Intrinsic<Vector, (args Vector:$a, Vector:$b),

                                (select (icmp_ule $a, $b), $a, $b)>,

              NameOverride<"vminq">;

  def vmaxqu: Intrinsic<Vector, (args Vector:$a, Vector:$b),

                                (select (icmp_uge $a, $b), $a, $b)>,

              NameOverride<"vmaxq">;

}

let params = T.Float in {

  def vminnmq: Intrinsic<Vector, (args Vector:$a, Vector:$b),

                               (IRIntBase<"minnum", [Vector]> $a, $b)>;

  def vmaxnmq: Intrinsic<Vector, (args Vector:$a, Vector:$b),

                               (IRIntBase<"maxnum", [Vector]> $a, $b)>;

}





multiclass contiguous_load<string mnemonic, PrimitiveType memtype,

                           list<Type> same_size, list<Type> wider> {

  // Intrinsics named with explicit memory and element sizes that match:

clang/include/clang/Basic/arm_mve_defs.td

+1 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ def fcmp_ge: IRBuilder<"CreateFCmpOGE">; 
def fcmp_lt: IRBuilder<"CreateFCmpOLT">;

def fcmp_le: IRBuilder<"CreateFCmpOLE">;

def splat: CGHelperFn<"ARMMVEVectorSplat">;

def select: IRBuilder<"CreateSelect">;



// A node that makes an Address out of a pointer-typed Value, by

// providing an alignment as the second argument.

clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c

0 → 100644
+65 −0
Original line number Diff line number Diff line 
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py

// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s

// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s



#include <arm_mve.h>



// CHECK-LABEL: @test_vmaxnmq_f16(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = tail call <8 x half> @llvm.maxnum.v8f16(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]])

// CHECK-NEXT:    ret <8 x half> [[TMP0]]

//

float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b)

{

#ifdef POLYMORPHIC

    return vmaxnmq(a, b);

#else /* POLYMORPHIC */

    return vmaxnmq_f16(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vmaxnmq_f32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = tail call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]])

// CHECK-NEXT:    ret <4 x float> [[TMP0]]

//

float32x4_t test_vmaxnmq_f32(float32x4_t a, float32x4_t b)

{

#ifdef POLYMORPHIC

    return vmaxnmq(a, b);

#else /* POLYMORPHIC */

    return vmaxnmq_f32(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vmaxnmq_m_f16(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = tail call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]], <8 x half> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <8 x half> [[TMP2]]

//

float16x8_t test_vmaxnmq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vmaxnmq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vmaxnmq_m_f16(inactive, a, b, p);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vmaxnmq_m_f32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <4 x float> [[TMP2]]

//

float32x4_t test_vmaxnmq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vmaxnmq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vmaxnmq_m_f32(inactive, a, b, p);

#endif /* POLYMORPHIC */

}

clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c

0 → 100644
+98 −0
Original line number Diff line number Diff line 
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py

// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s

// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s



#include <arm_mve.h>



// CHECK-LABEL: @test_vmaxq_s8(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = icmp slt <16 x i8> [[A:%.*]], [[B:%.*]]

// CHECK-NEXT:    [[TMP1:%.*]] = select <16 x i1> [[TMP0]], <16 x i8> [[B]], <16 x i8> [[A]]

// CHECK-NEXT:    ret <16 x i8> [[TMP1]]

//

int8x16_t test_vmaxq_s8(int8x16_t a, int8x16_t b)

{

#ifdef POLYMORPHIC

    return vmaxq(a, b);

#else /* POLYMORPHIC */

    return vmaxq_s8(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vmaxq_u16(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = icmp ult <8 x i16> [[A:%.*]], [[B:%.*]]

// CHECK-NEXT:    [[TMP1:%.*]] = select <8 x i1> [[TMP0]], <8 x i16> [[B]], <8 x i16> [[A]]

// CHECK-NEXT:    ret <8 x i16> [[TMP1]]

//

uint16x8_t test_vmaxq_u16(uint16x8_t a, uint16x8_t b)

{

#ifdef POLYMORPHIC

    return vmaxq(a, b);

#else /* POLYMORPHIC */

    return vmaxq_u16(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vmaxq_s32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = icmp slt <4 x i32> [[A:%.*]], [[B:%.*]]

// CHECK-NEXT:    [[TMP1:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[B]], <4 x i32> [[A]]

// CHECK-NEXT:    ret <4 x i32> [[TMP1]]

//

int32x4_t test_vmaxq_s32(int32x4_t a, int32x4_t b)

{

#ifdef POLYMORPHIC

    return vmaxq(a, b);

#else /* POLYMORPHIC */

    return vmaxq_s32(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vmaxq_m_u8(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = tail call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <16 x i8> [[TMP2]]

//

uint8x16_t test_vmaxq_m_u8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vmaxq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vmaxq_m_u8(inactive, a, b, p);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vmaxq_m_s16(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = tail call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <8 x i16> [[TMP2]]

//

int16x8_t test_vmaxq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vmaxq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vmaxq_m_s16(inactive, a, b, p);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vmaxq_m_u32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <4 x i32> [[TMP2]]

//

uint32x4_t test_vmaxq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vmaxq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vmaxq_m_u32(inactive, a, b, p);

#endif /* POLYMORPHIC */

}

clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c

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+65 −0
Original line number Diff line number Diff line 
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py

// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s

// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s



#include <arm_mve.h>



// CHECK-LABEL: @test_vminnmq_f16(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = tail call <8 x half> @llvm.minnum.v8f16(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]])

// CHECK-NEXT:    ret <8 x half> [[TMP0]]

//

float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b)

{

#ifdef POLYMORPHIC

    return vminnmq(a, b);

#else /* POLYMORPHIC */

    return vminnmq_f16(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vminnmq_f32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]])

// CHECK-NEXT:    ret <4 x float> [[TMP0]]

//

float32x4_t test_vminnmq_f32(float32x4_t a, float32x4_t b)

{

#ifdef POLYMORPHIC

    return vminnmq(a, b);

#else /* POLYMORPHIC */

    return vminnmq_f32(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vminnmq_m_f16(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]], <8 x half> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <8 x half> [[TMP2]]

//

float16x8_t test_vminnmq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vminnmq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vminnmq_m_f16(inactive, a, b, p);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vminnmq_m_f32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <4 x float> [[TMP2]]

//

float32x4_t test_vminnmq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vminnmq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vminnmq_m_f32(inactive, a, b, p);

#endif /* POLYMORPHIC */

}