Commit 4f8259bd authored by Nikita Popov's avatar Nikita Popov
Browse files

[Thumb] Fix invalid symbol redefinition due to duplicated jumptable (PR42760) 

Fix for https://bugs.llvm.org/show_bug.cgi?id=42760. A tBR_JTr
instruction is duplicated by tail duplication, which results in
the same jumptable with the same label being emitted twice.

Fix this by marking tBR_JTr as not duplicable. The corresponding
ARM/Thumb instructions are already marked as not duplicable.
Additionally also mark tTBB_JT and tTBH_JT to be consistent with
Thumb2, even though this shouldn't be strictly necessary.

Differential Revision: https://reviews.llvm.org/D65606

llvm-svn: 367753
parent a67d81e4

llvm/lib/Target/ARM/ARMInstrThumb.td

+2 −1
Original line number Diff line number Diff line
@@ -592,6 +592,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 
                      [(ARMbrjt tGPR:$target, tjumptable:$jt)]>,

                      Sched<[WriteBrTbl]> {

    let Size = 2;

    let isNotDuplicable = 1;

    list<Predicate> Predicates = [IsThumb, IsThumb1Only];

  }

}
@@ -1471,7 +1472,7 @@ def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 
// Thumb-1 doesn't have the TBB or TBH instructions, but we can synthesize them

// and make use of the same compressed jump table format as Thumb-2.

let Size = 2, isBranch = 1, isTerminator = 1, isBarrier = 1,

    isIndirectBranch = 1 in {

    isIndirectBranch = 1, isNotDuplicable = 1 in {

def tTBB_JT : tPseudoInst<(outs),

        (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0,

         IIC_Br, []>, Sched<[WriteBr]>;

llvm/test/CodeGen/Thumb/pr42760.ll

0 → 100644
+56 −0
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -mtriple=thumbv6m-none-unknown-eabi -tail-dup-placement-threshold=3 < %s | FileCheck %s



define hidden void @test() {

; CHECK-LABEL: test:

; CHECK:       @ %bb.0: @ %entry

; CHECK-NEXT:    movs r0, #1

; CHECK-NEXT:    lsls r1, r0, #2

; CHECK-NEXT:    b .LBB0_2

; CHECK-NEXT:  .LBB0_1: @ %bb2

; CHECK-NEXT:    @ in Loop: Header=BB0_2 Depth=1

; CHECK-NEXT:    cmp r0, #0

; CHECK-NEXT:    bne .LBB0_6

; CHECK-NEXT:  .LBB0_2: @ %switch

; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1

; CHECK-NEXT:    adr r2, .LJTI0_0

; CHECK-NEXT:    ldr r2, [r2, r1]

; CHECK-NEXT:    mov pc, r2

; CHECK-NEXT:  @ %bb.3:

; CHECK-NEXT:    .p2align 2

; CHECK-NEXT:  .LJTI0_0:

; CHECK-NEXT:    .long .LBB0_6+1

; CHECK-NEXT:    .long .LBB0_4+1

; CHECK-NEXT:    .long .LBB0_6+1

; CHECK-NEXT:    .long .LBB0_5+1

; CHECK-NEXT:  .LBB0_4: @ %switch

; CHECK-NEXT:    @ in Loop: Header=BB0_2 Depth=1

; CHECK-NEXT:    b .LBB0_1

; CHECK-NEXT:  .LBB0_5: @ %bb

; CHECK-NEXT:    @ in Loop: Header=BB0_2 Depth=1

; CHECK-NEXT:    cmp r0, #0

; CHECK-NEXT:    beq .LBB0_1

; CHECK-NEXT:  .LBB0_6: @ %dead

entry:

  br label %switch



switch:                                           ; preds = %bb2, %entry

  switch i32 undef, label %dead2 [

    i32 0, label %dead

    i32 1, label %bb2

    i32 2, label %dead

    i32 3, label %bb

  ]



dead:                                             ; preds = %bb2, %bb, %switch, %switch

  unreachable



dead2:                                            ; preds = %switch

  unreachable



bb:                                               ; preds = %switch

  br i1 undef, label %dead, label %bb2



bb2:                                              ; preds = %bb, %switch

  br i1 undef, label %dead, label %switch

}