Commit 4eb4f896 authored by Craig Topper's avatar Craig Topper
Browse files

[RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64. 

As far as I know 32 bits arguments and returns on RV64 are always
sign extended to i64. So I think we should be taking this into
account around libcalls.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D95285
parent 193cda10

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+7 −0
Original line number Diff line number Diff line
@@ -4250,6 +4250,13 @@ bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const { 
  return true;

}



bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {

  if (Subtarget.is64Bit() && Type == MVT::i32)

    return true;



  return IsSigned;

}



bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,

                                                 SDValue C) const {

  // Check integral scalar types.

llvm/lib/Target/RISCV/RISCVISelLowering.h

+1 −0
Original line number Diff line number Diff line
@@ -217,6 +217,7 @@ public: 
  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;



  bool shouldExtendTypeInLibCall(EVT Type) const override;

  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;



  /// Returns the register with the specified architectural or ABI name. This

  /// method is necessary to lower the llvm.read_register.* and

llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll

+2 −8
Original line number Diff line number Diff line
@@ -80,7 +80,6 @@ define i32 @flt_s(float %a, float %b) nounwind { 
; RV64I-NEXT:    addi sp, sp, -16

; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill

; RV64I-NEXT:    call __ltsf2@plt

; RV64I-NEXT:    sext.w a0, a0

; RV64I-NEXT:    slti a0, a0, 0

; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload

; RV64I-NEXT:    addi sp, sp, 16
@@ -96,7 +95,6 @@ define i32 @fle_s(float %a, float %b) nounwind { 
; RV64I-NEXT:    addi sp, sp, -16

; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill

; RV64I-NEXT:    call __lesf2@plt

; RV64I-NEXT:    sext.w a0, a0

; RV64I-NEXT:    slti a0, a0, 1

; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload

; RV64I-NEXT:    addi sp, sp, 16
@@ -112,7 +110,6 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind { 
; RV64I-NEXT:    addi sp, sp, -16

; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill

; RV64I-NEXT:    call __gtsf2@plt

; RV64I-NEXT:    sext.w a0, a0

; RV64I-NEXT:    sgtz a0, a0

; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload

; RV64I-NEXT:    addi sp, sp, 16
@@ -128,7 +125,6 @@ define i32 @fcmp_oge(float %a, float %b) nounwind { 
; RV64I-NEXT:    addi sp, sp, -16

; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill

; RV64I-NEXT:    call __gesf2@plt

; RV64I-NEXT:    sext.w a0, a0

; RV64I-NEXT:    addi a1, zero, -1

; RV64I-NEXT:    slt a0, a1, a0

; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
@@ -214,8 +210,7 @@ define float @fcvt_s_wu(i32 %a) nounwind { 
; RV64I:       # %bb.0:

; RV64I-NEXT:    addi sp, sp, -16

; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill

; RV64I-NEXT:    slli a0, a0, 32

; RV64I-NEXT:    srli a0, a0, 32

; RV64I-NEXT:    sext.w a0, a0

; RV64I-NEXT:    call __floatunsisf@plt

; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload

; RV64I-NEXT:    addi sp, sp, 16
@@ -675,8 +670,7 @@ define float @fpowi_s(float %a, i32 %b) nounwind { 
; RV64I:       # %bb.0:

; RV64I-NEXT:    addi sp, sp, -16

; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill

; RV64I-NEXT:    slli a1, a1, 32

; RV64I-NEXT:    srli a1, a1, 32

; RV64I-NEXT:    sext.w a1, a1

; RV64I-NEXT:    call __powisf2@plt

; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload

; RV64I-NEXT:    addi sp, sp, 16