ReleaseNotes: remove in-progress warnings, tidy up a bit

====================================================

Extra Clang Tools 10.0.0 (In-Progress) Release Notes

====================================================

======================================

Extra Clang Tools 10.0.0 Release Notes

======================================

.. contents::

   :local:

Written by the `LLVM Team <https://llvm.org/>`_

.. warning::

   These are in-progress notes for the upcoming Extra Clang Tools 10 release.

   Release notes for previous releases can be found on

   `the Download Page <https://releases.llvm.org/download.html>`_.

Introduction

============

the latest release, please see the `Clang Web Site <https://clang.llvm.org>`_ or

the `LLVM Web Site <https://llvm.org>`_.

Note that if you are reading this file from a Subversion checkout or the

main Clang web page, this document applies to the *next* release, not

the current one. To see the release notes for a specific release, please

see the `releases page <https://llvm.org/releases/>`_.

What's New in Extra Clang Tools 10.0.0?

=======================================

here. Generic improvements to Extra Clang Tools as a whole or to its underlying

infrastructure are described first, followed by tool-specific sections.

Major New Features

------------------

...

Improvements to clangd

----------------------

- clangd can be more easily used remotely or in a docker container.

  The `--path-mappings` flag translates between local and remote paths.

  The ``--path-mappings`` flag translates between local and remote paths.

- Experimental support for renaming across files (behind the

  `--cross-file-rename` flag).

  ``--cross-file-rename`` flag).

- Hover now exposes more information, including the type of symbols and the

  value of constant expressions.

- Semantic highlighting is more robust, highlights more types of tokens, and

  as an extension provides information about inactive preprocessor regions.

- Code completion results now include an extension field `score`.

- Code completion results now include an extension field ``score``.

  This allows clients to incorporate clangd quality signals when re-ranking code

  completion after client-side fuzzy-matching.

- :doc:`clang-doc <clang-doc>` now generates documentation in HTML format.

Improvements to clang-query

---------------------------

The improvements are...

Improvements to clang-rename

----------------------------

The improvements are...

Improvements to clang-tidy

--------------------------

- The 'objc-avoid-spinlock' check was renamed to :doc:`darwin-avoid-spinlock

  <clang-tidy/checks/darwin-avoid-spinlock>`

Improvements to include-fixer

-----------------------------

The improvements are...

Improvements to clang-include-fixer

-----------------------------------

The improvements are...

Improvements to modularize

--------------------------

The improvements are...

Improvements to pp-trace

------------------------

The improvements are...

Clang-tidy visual studio plugin

-------------------------------

========================================

Clang 10.0.0 (In-Progress) Release Notes

========================================

==========================

Clang 10.0.0 Release Notes

==========================

.. contents::

   :local:

Written by the `LLVM Team <https://llvm.org/>`_

.. warning::

   These are in-progress notes for the upcoming Clang 10 release.

   Release notes for previous releases can be found on

   `the Download Page <https://releases.llvm.org/download.html>`_.

Introduction

============

latest release, please see the `Clang Web Site <https://clang.llvm.org>`_ or the

`LLVM Web Site <https://llvm.org>`_.

Note that if you are reading this file from a Subversion checkout or the

main Clang web page, this document applies to the *next* release, not

the current one. To see the release notes for a specific release, please

see the `releases page <https://llvm.org/releases/>`_.

What's New in Clang 10.0.0?

===========================

- -Wtautological-overlap-compare will warn on negative numbers and non-int

  types.

- -Wtautological-compare for self comparisons and

  -Wtautological-overlap-compare will now look through member and array

  access to determine if two operand expressions are the same.

- -Wtautological-bitwise-compare is a new warning group.  This group has the

  current warning which diagnoses the tautological comparison of a bitwise

  operation and a constant. The group also has the new warning which diagnoses

  when a bitwise-or with a non-negative value is converted to a bool, since

  that bool will always be true.

- -Wbitwise-conditional-parentheses will warn on operator precedence issues

  when mixing bitwise-and (&) and bitwise-or (|) operator with the

  conditional operator (?:).

- -Wrange-loop-analysis got several improvements. It no longer warns about a

  copy being made when the result is bound to an rvalue reference. It no longer

  warns when an object of a small, trivially copyable type is copied. The

  warning now offers fixits. Excluding -Wrange-loop-bind-reference it is now

  part of -Wall. To reduce the number of false positives the diagnostic is

  disabled in macros and template instantiations.

- -Wmisleading-indentation has been added. This warning is similar to the GCC

  warning of the same name. It warns about statements that are indented as if

  they were part of a if/else/for/while statement but are not semantically

  part of that if/else/for/while.

- -Wbitwise-op-parentheses and -Wlogical-op-parentheses are disabled by default.

Non-comprehensive list of changes in this release

  learned to sanitize pre/post increment/decrement of types with bit width

  smaller than ``int``.

- For X86 target, -march=skylake-avx512, -march=icelake-client,

* For X86 target, -march=skylake-avx512, -march=icelake-client,

  -march=icelake-server, -march=cascadelake, -march=cooperlake will default to

  not using 512-bit zmm registers in vectorized code unless 512-bit intrinsics

  are used in the source code. 512-bit operations are known to cause the CPUs

  please let us know if you encounter a situation where you need to specify this

  flag for correct program behavior.

- The `-ffixed-xX` flags now work on RISC-V. These reserve the corresponding

- The ``-ffixed-xX`` flags now work on RISC-V. These reserve the corresponding

  general-purpose registers.

- RISC-V has added `-mcmodel=medany` and `-mcmodel=medlow` as aliases for

  `-mcmodel=small` and `-mcmodel=medium` respectively. Preprocessor definitions

  for `__riscv_cmodel_medlow` and `__riscv_cmodel_medany` have been corrected.

- RISC-V has added ``-mcmodel=medany`` and ``-mcmodel=medlow`` as aliases for

  ``-mcmodel=small`` and ``-mcmodel=medium`` respectively. Preprocessor definitions

  for ``__riscv_cmodel_medlow`` and ``__riscv_cmodel_medany`` have been corrected.

- ``-fmacro-prefix-map=OLD=NEW`` substitutes directory prefix ``OLD`` for

  ``NEW`` in predefined preprocessor macros such as ``__FILE__``. This helps

- -mmpx used to enable the __MPX__ preprocessor define for the Intel MPX

  instructions. There were no MPX intrinsics.

- -mno-mpx used to disable -mmpx and is the default behavior.

- -fconcepts-ts previously used to enable experimental concepts support. Use

  -std=c++2a instead to enable Concepts support.

- ...

Modified Compiler Flags

-----------------------

- RISC-V now supports multilibs in baremetal environments. This support does not

  extend to supporting multilib aliases.

New Pragmas in Clang

--------------------

- ...

Attribute Changes in Clang

--------------------------

  functions using the new ``__declspec(guard(nocf))`` modifier.

C Language Changes in Clang

---------------------------

- ...

C11 Feature Support

^^^^^^^^^^^^^^^^^^^

...

C++ Language Changes in Clang

-----------------------------

  how it behaved in previous Clang versions, a warning is emitted for this

  combination.

C++1z Feature Support

^^^^^^^^^^^^^^^^^^^^^

...

Objective-C Language Changes in Clang

-------------------------------------

- Added basic analysis for use of the uninitialized variables in clauses.

- Bug fixes.

CUDA Support in Clang

---------------------

- ...

Internal API Changes

--------------------

  statically linking clang's components. This option will reduce the size of

  binary distributions at the expense of compiler performance.

- ...

AST Matchers

------------

- ...

clang-format

------------

        return getelementpointer_inbounds(base, offset);

      }

Core Analysis Improvements

==========================

- ...

New Issues Found

================

- ...

Python Binding Changes

----------------------

The following methods have been added:

-  ...

Significant Known Problems

==========================

Additional Information

======================

=========================================

Libc++ 10.0.0 (In-Progress) Release Notes

=========================================

===========================

Libc++ 10.0.0 Release Notes

===========================

.. contents::

   :local:

Written by the `Libc++ Team <https://libcxx.llvm.org>`_

.. warning::

   These are in-progress notes for the upcoming libc++ 10 release.

   Release notes for previous releases can be found on

   `the Download Page <https://releases.llvm.org/download.html>`_.

Introduction

============

For more information about libc++, please see the `Libc++ Web Site

<https://libcxx.llvm.org>`_ or the `LLVM Web Site <https://llvm.org>`_.

Note that if you are reading this file from a Subversion checkout or the

main Libc++ web page, this document applies to the *next* release, not

the current one. To see the release notes for a specific release, please

see the `releases page <https://llvm.org/releases/>`_.

What's New in Libc++ 10.0.0?

============================

-----

- Fixed use of non-default locales on Windows

New Features

------------

API Changes

-----------

- ...

.. contents::

    :local:

.. warning::

   These are in-progress notes for the upcoming LLVM 10.0.0 release.

   Release notes for previous releases can be found on

   `the Download Page <https://releases.llvm.org/download.html>`_.

Introduction

============

  could cause subtle bugs.

  (`D70468 <https://reviews.llvm.org/D70468>`_)

COFF Improvements

-----------------

* ...

MinGW Improvements

------------------

  (which can happen for the default-null symbol for weak symbols)

  (`1737cc750c46 <https://reviews.llvm.org/rG1737cc750c46>`)

MachO Improvements

------------------

* Item 1.

WebAssembly Improvements

------------------------

.. contents::

    :local:

.. warning::

   These are in-progress notes for the upcoming LLVM 10 release.

   Release notes for previous releases can be found on

   `the Download Page <https://releases.llvm.org/download.html>`_.

Introduction

============

<https://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send

them.

Note that if you are reading this file from a Subversion checkout or the main

LLVM web page, this document applies to the *next* release, not the current

one.  To see the release notes for a specific release, please see the `releases

page <https://llvm.org/releases/>`_.

Non-comprehensive list of changes in this release

=================================================

.. NOTE

   For small 1-3 sentence descriptions, just add an entry at the end of

   this list. If your description won't fit comfortably in one bullet

   point (e.g. maybe you would like to give an example of the

   functionality, or simply have a lot to talk about), see the `NOTE` below

   for adding a new subsection.

* The ISD::FP_ROUND_INREG opcode and related code was removed from SelectionDAG.

* Enabled MemorySSA as a loop dependency. Since

  `r370957 <https://reviews.llvm.org/rL370957>`_

  (`D58311 <https://reviews.llvm.org/D58311>`_ ``[MemorySSA & LoopPassManager]

  AliasSetTracker usage with MemorySSA without any performance penalties.

  The fact that MemorySSA is now preserved by and available in a series of loop

  passes, also opens up opportunities for its use in those respective passes.

* The BasicBlockPass, BBPassManager and all their uses were deleted in

  `this revision <https://reviews.llvm.org/rG9f0ff0b2634bab6a5be8dace005c9eb24d386dd1>`_.

* The LLVM_BUILD_LLVM_DYLIB and LLVM_LINK_LLVM_DYLIB CMake options are no longer

  available on Windows.

.. NOTE

   If you would like to document a larger change, then you can add a

   subsection about it right here. You can copy the following boilerplate

   and un-indent it (the indentation causes it to be inside this comment).

   Special New Feature

   -------------------

   Makes programs 10x faster by doing Special New Thing.

* As per :ref:`LLVM Language Reference Manual <i_getelementptr>`,

  ``getelementptr inbounds`` can not change the null status of a pointer,

  meaning it can not produce non-null pointer given null base pointer, and

  Undefined Behaviour Sanitizer ``-fsanitize=pointer-overflow`` check

  will now catch such cases.

* Windows Control Flow Guard: the ``-cfguard`` option now emits CFG checks on

  indirect function calls. The previous behavior is still available with the

  ``-cfguard-nochecks`` option. Note that this feature should always be used

  that correctly converted 80-90% of Clang tests. Some manual work will almost

  certainly still be needed.

* A new `freeze` instruction is added. The `freeze` instruction is used to stop

* A new ``freeze`` instruction is added. The ``freeze`` instruction is used to stop

  IR-level propagation of undef and poison values. Currently its support is

  preliminary; a freeze-equivalent operation for SelDag/MIR needs to be added.

Changes to building LLVM

------------------------

...

Changes to the AArch64 Backend

------------------------------

- Added support for Cortex-A65, Cortex-A65AE, Neoverse E1 and Neoverse N1 cores.

- With a few more bugs fixed in the LLVM 10 release, clang-cl can now target windows-on-Arm well, demonstrated by building complex pieces of software such as Chromium and the Electron framework.

- Support for -fpatchable-function-entry was added.

* Added support for Cortex-A65, Cortex-A65AE, Neoverse E1 and Neoverse N1 cores.

* With a few more bugs fixed in the LLVM 10 release, clang-cl can now target windows-on-Arm well, demonstrated by building complex pieces of software such as Chromium and the Electron framework.

* Support for -fpatchable-function-entry was added.

Changes to the ARM Backend

--------------------------

- Optimized Armv8.1-M code generation, including generating Low Overhead Loops.

- Added auto-vectorization for the Armv8.1-M MVE vector extension.

- Support was added for inline asm constraints s,j,x,N,O.

* Optimized Armv8.1-M code generation, including generating Low Overhead Loops.

* Added auto-vectorization for the Armv8.1-M MVE vector extension.

* Support was added for inline asm constraints s,j,x,N,O.

Changes to the MIPS Target

* Improved support for ``octeon`` and added support for ``octeon+``

  MIPS-family CPU.

* ``min``, ``max``, ``umin``, ``umax`` atomics now supported on MIPS targets.

* Now PC-relative relocations are generated for ``.eh_frame`` sections when

  possible. That allows to link MIPS binaries without having to pass the

  ``-Wl,-z,notext`` option.

* Fix evaluating J-format branch (``j``, ``jal``, ...) targets when the

  instruction is not in the first 256 MB region.

* Fixed ``jal``, ``sc``, ``scs``, ``ll``, ``lld``, ``la``, ``lw``, ``sw``

  instructions expanding. Now they accept more types of expression as arguments,

  correctly handle load/store for ``XGOT`` model, expand using less instructions

  or registers.

* Initial MIPS support has been added to ``llvm-exegesis``.

* Generates ``_mcount`` calls using proper MIPS ABI.

* Improved support of GlobalISel instruction selection framework. This feature

  is still in experimental state for MIPS targets though.

Optimization:

  *  Improved register pressure estimates in the loop vectorizer based on type

  *  Improved the PowerPC cost model for the vectorizer

  *  Enabled vectorization of math routines on PowerPC using MASSV (Mathematical Acceleration SubSystem) library

compiler-rt:

Codegen:

   *  Optimized memory access instructions in loops (pertaining to update-form instructions and address computation)

   *  Added options to disable hoisting instructions to hotter blocks based on statically or profile-based block hotness estimates

   *  Code generation improvements (particularly with floating point and vector code as well as handling condition registers)

   *  Various infrastructural improvements, code refactoring, and bug fixes

   *  Optimized handling of control flow based on multiple comparison of same values

Tools:

  *   llvm-readobj supports displaying file header, section headers, symbol table and relocation entries for XCOFF object files

  *   llvm-objdump supports disassembling physical sections for XCOFF object files

* Added support for the ``-march=z15`` and ``-mtune=z15`` command line options

  (as aliases to the existing ``-march=arch13`` and ``-mtune=arch13`` options).

* Added support for the ``-march=native`` command line option.

* Added support for the ``-mfentry``, ``-mnop-mcount``, and ``-mrecord-mcount``

  command line options.

* Added support for the GHC calling convention.

* Miscellaneous codegen enhancements, in particular to enable better

  reuse of condition code values and improved use of conditional

  move instructions.

  now stored in the lower bits of an xmm register and the upper bits are

  undefined. Previously the elements were spread apart with undefined bits in

  between them.

* v32i8 and v64i8 vectors with AVX512F enabled, but AVX512BW disabled will now

  be passed in ZMM registers for calls and returns. Previously they were passed

  in two YMM registers. Old behavior can be enabled by passing

  -x86-enable-old-knl-abi

* -mprefer-vector-width=256 is now the default behavior skylake-avx512 and later

  Intel CPUs. This tries to limit the use of 512-bit registers which can cause a

  decrease in CPU frequency on these CPUs. This can be re-enabled by passing

  -mprefer-vector-width=512 to clang or passing -mattr=-prefer-256-bit to llc.

* Deprecated the mpx feature flag for the Intel MPX instructions. There were no

  intrinsics for this feature. This change only this effects the results

  returned by getHostCPUFeatures on CPUs that implement the MPX instructions.

* The feature flag fast-partial-ymm-or-zmm-write which previously disabled

  vzeroupper insertion has been removed. It has been replaced with a vzeroupper

  feature flag which has the opposite polarity. So -vzeroupper has the same

  effect as +fast-partial-ymm-or-zmm-write.

Changes to the AMDGPU Target

-----------------------------

Changes to the AVR Target

-----------------------------

 During this release ...

Changes to the WebAssembly Target

---------------------------------

* __attribute__((used)) no longer implies that a symbol is exported, for

  consistency with other targets.

* Multivalue function signatures are now supported in WebAssembly object files

* The new `atomic.fence` instruction is now supported

* The new ``atomic.fence`` instruction is now supported

* Thread-Local Storage (TLS) is now supported.

* SIMD support is significantly expanded.

Changes to the Windows Target

----------------------------

New Features:

* The Machine Outliner is now supported, but not enabled by default.

* Shrink-wrapping is now supported.

* The Machine Scheduler has been enabled and scheduler descriptions for the

  Rocket micro-architecture have been added, covering both 32- and 64-bit Rocket

  cores.

* This release lays the groundwork for enabling LTO in a future LLVM release.

  In particular, LLVM now uses a new `target-abi` module metadata item to

  In particular, LLVM now uses a new ``target-abi`` module metadata item to

  represent the chosen RISC-V psABI variant. Frontends should add this module

  flag to prevent ABI lowering problems when LTO is enabled in a future LLVM

  release.

* Support has been added for assembling RVC HINT instructions.

* Added code lowering for half-precision floats.

* The `fscsr` and `frcsr` (`fssr`, `frsr`) obsolete aliases have been added to

* The ``fscsr`` and ``frcsr`` (``fssr``, ``frsr``) obsolete aliases have been added to

  the assembler for use in legacy code.

* The stack can now be realigned even when there are variable-sized objects in

  the same frame.

* fastcc is now supported. This is a more efficient, unstandardised, calling

  convention for calls to private leaf functions in the same IR module.

* llvm-objdump now supports `-M no-aliases` and `-M numeric` for altering the

* llvm-objdump now supports ``-M no-aliases`` and ``-M numeric`` for altering the

  dumped assembly. These match the behaviour of GNU objdump, respectively

  disabling instruction aliases and printing the numeric register names rather

  than the ABI register names.

Improvements:

* Trap and Debugtrap now lower to RISC-V-specific trap instructions.

* LLVM IR Inline assembly now supports using ABI register names and using

  floating point registers in constraints.

* Stack Pointer adjustments have been changed to better match RISC-V's immediates.

* `ra` (`x1`) can now be used as a callee-saved register.

* ``ra`` (``x1``) can now be used as a callee-saved register.

* The assembler now suggests spelling corrections for unknown assembly

  mnemonics.

* Stack offsets of greater than 32-bits are now accepted on RV64.

* Variadic functions can now be tail-call optimised, as long as they do not use

  stack memory for passing arguments.

* Code generation has been changed for 32-bit arithmetic operations on RV64 to

  reduce sign-extensions.

Bug Fixes:

* There was an issue with register preservation after calls in interrupt

  handlers, where some registers were marked as preserved even though they were

  not being preserved by the call. This has been corrected, and now only

  callee-saved registers are live over a function call in an interrupt handler

  (just like calls in regular functions).

* Atomic instructions now only accept GPRs (plus an offset) in memory operands.

* Fixed some issues with evaluation of relocations and fixups.

* The error messages around missing RISC-V extensions in the assembler have been

  improved.

* The error messages around unsupported relocations have been improved.

* Non-PIC code no longer forces Local Exec TLS.

* There have been some small changes to the code generation for atomic

  operations.

* RISC-V no longer emits incorrect CFI directives in function prologs and

  epilogs.

* RV64 no longer clears the upper bits when returning complex types from

  libcalls using the LP64 psABI.

Compiler-RT:

* RISC-V (both 64-bit and 32-bit) is now supported by compiler-rt, allowing

  crtbegin and crtend to be built.

* The Sanitizers now support 64-bit RISC-V on linux.

Changes to the OCaml bindings

-----------------------------

* The Sanitizers now support 64-bit RISC-V on linux.

  to Debug information in LLVM IR.

Changes to the DAG infrastructure

---------------------------------

Changes to LLDB

===============

* Tab completions for command options now also provide a description for each option.

* Fixed that printing structs/classes with the `expression` command sometimes did not

* Fixed that printing structs/classes with the ``expression`` command sometimes did not

  print the members/contents of the class.

* Improved support for using classes with bit-field members in the expression evaluator.