Loading llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +6 −1 Original line number Diff line number Diff line Loading @@ -1389,7 +1389,8 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const { // Check that CPSR isn't set between the comparison instruction and the one we // want to change. MachineBasicBlock::const_iterator I = CmpInstr, E = MI; MachineBasicBlock::const_iterator I = CmpInstr, E = MI, B = MI->getParent()->begin(); --I; for (; I != E; --I) { const MachineInstr &Instr = *I; Loading @@ -1403,6 +1404,10 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const { if (MO.getReg() == ARM::CPSR) return false; } if (I == B) // The 'and' is below the comparison instruction. return false; } // Set the "zero" bit in CPSR. Loading Loading
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +6 −1 Original line number Diff line number Diff line Loading @@ -1389,7 +1389,8 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const { // Check that CPSR isn't set between the comparison instruction and the one we // want to change. MachineBasicBlock::const_iterator I = CmpInstr, E = MI; MachineBasicBlock::const_iterator I = CmpInstr, E = MI, B = MI->getParent()->begin(); --I; for (; I != E; --I) { const MachineInstr &Instr = *I; Loading @@ -1403,6 +1404,10 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const { if (MO.getReg() == ARM::CPSR) return false; } if (I == B) // The 'and' is below the comparison instruction. return false; } // Set the "zero" bit in CPSR. Loading