Unverified Commit 46cb8d9a authored by AdityaK's avatar AdityaK Committed by GitHub
Browse files

[TSAN] add support for riscv64 (#68735)

Implements for sv39 and sv48 VMA layout.

Userspace only has access to the bottom half of vma range. The top half
is used by kernel. There is no dedicated vsyscall or heap segment.
PIE program is allocated to start at TASK_SIZE/3*2. Maximum ASLR is
ARCH_MMAP_RND_BITS_MAX+PAGE_SHIFT=24+12=36 Loader, vdso and other
libraries are allocated below stack from the top.

Also change RestoreAddr to use 4 bits to accommodate MappingRiscv64_48

Reviewed by: MaskRay, dvyukov, asb, StephenFan, luismarques, jrtc27,
hiraditya, vitalybuka

Differential Revision: https://reviews.llvm.org/D145214



D145214 was reverted because one file was missing in the latest commit.
Luckily the file was there in the previous commit, probably the author
missed uploading that file with latest commit.

Co-authored-by: default avatarAlex Fan <alex.fan.q@gmail.com>
parent b90fcafc
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+1 −1
Original line number Diff line number Diff line
@@ -801,7 +801,7 @@ SanitizerMask Linux::getSupportedSanitizers() const {
      IsRISCV64 || IsSystemZ || IsHexagon || IsLoongArch64)
    Res |= SanitizerKind::Leak;
  if (IsX86_64 || IsMIPS64 || IsAArch64 || IsPowerPC64 || IsSystemZ ||
      IsLoongArch64)
      IsLoongArch64 || IsRISCV64)
    Res |= SanitizerKind::Thread;
  if (IsX86_64 || IsSystemZ)
    Res |= SanitizerKind::KernelMemory;
+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ set(ALL_PROFILE_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${PPC32} ${PPC
    ${MIPS32} ${MIPS64} ${S390X} ${SPARC} ${SPARCV9} ${HEXAGON}
    ${RISCV32} ${RISCV64} ${LOONGARCH64})
set(ALL_TSAN_SUPPORTED_ARCH ${X86_64} ${MIPS64} ${ARM64} ${PPC64} ${S390X}
    ${LOONGARCH64})
    ${LOONGARCH64} ${RISCV64})
set(ALL_UBSAN_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${RISCV64}
    ${MIPS32} ${MIPS64} ${PPC64} ${S390X} ${SPARC} ${SPARCV9} ${HEXAGON}
    ${LOONGARCH64})
+1 −1
Original line number Diff line number Diff line
@@ -303,7 +303,7 @@
#    define SANITIZER_MMAP_RANGE_SIZE FIRST_32_SECOND_64(1ULL << 32, 1ULL << 40)
#  endif
#elif SANITIZER_RISCV64
#  define SANITIZER_MMAP_RANGE_SIZE FIRST_32_SECOND_64(1ULL << 32, 1ULL << 38)
#  define SANITIZER_MMAP_RANGE_SIZE FIRST_32_SECOND_64(1ULL << 32, 1ULL << 47)
#elif defined(__aarch64__)
#  if SANITIZER_APPLE
#    if SANITIZER_OSX || SANITIZER_IOSSIM
+4 −0
Original line number Diff line number Diff line
@@ -220,6 +220,10 @@ else()
      set(TSAN_ASM_SOURCES
        tsan_rtl_mips64.S
        )
    elseif(arch MATCHES "riscv64")
      set(TSAN_ASM_SOURCES
        tsan_rtl_riscv64.S
        )
    elseif(arch MATCHES "s390x")
      set(TSAN_ASM_SOURCES
        tsan_rtl_s390x.S
+2 −0
Original line number Diff line number Diff line
@@ -81,6 +81,8 @@ struct ucontext_t {
#define PTHREAD_ABI_BASE  "GLIBC_2.17"
#elif SANITIZER_LOONGARCH64
#define PTHREAD_ABI_BASE  "GLIBC_2.36"
#elif SANITIZER_RISCV64
#  define PTHREAD_ABI_BASE "GLIBC_2.27"
#endif

extern "C" int pthread_attr_init(void *attr);
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