Loading llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +9 −0 Original line number Diff line number Diff line Loading @@ -206,6 +206,15 @@ unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) { return (SEW * 8) / LMul; } RISCVII::VLMUL RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) { unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL); unsigned EMULFixedPoint = (EEW * 8) / Ratio; bool Fractional = EMULFixedPoint < 8; unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8; return RISCVVType::encodeLMUL(EMUL, Fractional); } // Include the auto-generated portion of the compress emitter. #define GEN_UNCOMPRESS_INSTR #define GEN_COMPRESS_INSTR Loading llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +2 −0 Original line number Diff line number Diff line Loading @@ -535,6 +535,8 @@ void printVType(unsigned VType, raw_ostream &OS); unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul); RISCVII::VLMUL getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW); } // namespace RISCVVType namespace RISCVRVC { Loading llvm/unittests/Target/RISCV/CMakeLists.txt +1 −0 Original line number Diff line number Diff line Loading @@ -13,6 +13,7 @@ set(LLVM_LINK_COMPONENTS add_llvm_target_unittest(RISCVTests MCInstrAnalysisTest.cpp RISCVBaseInfoTest.cpp ) set_property(TARGET RISCVTests PROPERTY FOLDER "Tests/UnitTests/TargetTests") llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp 0 → 100644 +34 −0 Original line number Diff line number Diff line //===- RISCVBaseInfoTest.cpp - RISCVBaseInfo unit tests ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "MCTargetDesc/RISCVBaseInfo.h" #include "gtest/gtest.h" using namespace llvm; namespace { TEST(RISCVBaseInfo, CheckSameRatioLMUL) { // Smaller LMUL. EXPECT_EQ(RISCVII::LMUL_1, RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_2, 8)); EXPECT_EQ(RISCVII::LMUL_F2, RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_1, 8)); // Smaller fractional LMUL. EXPECT_EQ(RISCVII::LMUL_F8, RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_F4, 8)); // Bigger LMUL. EXPECT_EQ(RISCVII::LMUL_2, RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_1, 16)); EXPECT_EQ(RISCVII::LMUL_1, RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16)); // Bigger fractional LMUL. EXPECT_EQ(RISCVII::LMUL_F2, RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16)); } } // namespace Loading
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +9 −0 Original line number Diff line number Diff line Loading @@ -206,6 +206,15 @@ unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) { return (SEW * 8) / LMul; } RISCVII::VLMUL RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) { unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL); unsigned EMULFixedPoint = (EEW * 8) / Ratio; bool Fractional = EMULFixedPoint < 8; unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8; return RISCVVType::encodeLMUL(EMUL, Fractional); } // Include the auto-generated portion of the compress emitter. #define GEN_UNCOMPRESS_INSTR #define GEN_COMPRESS_INSTR Loading
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +2 −0 Original line number Diff line number Diff line Loading @@ -535,6 +535,8 @@ void printVType(unsigned VType, raw_ostream &OS); unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul); RISCVII::VLMUL getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW); } // namespace RISCVVType namespace RISCVRVC { Loading
llvm/unittests/Target/RISCV/CMakeLists.txt +1 −0 Original line number Diff line number Diff line Loading @@ -13,6 +13,7 @@ set(LLVM_LINK_COMPONENTS add_llvm_target_unittest(RISCVTests MCInstrAnalysisTest.cpp RISCVBaseInfoTest.cpp ) set_property(TARGET RISCVTests PROPERTY FOLDER "Tests/UnitTests/TargetTests")
llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp 0 → 100644 +34 −0 Original line number Diff line number Diff line //===- RISCVBaseInfoTest.cpp - RISCVBaseInfo unit tests ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "MCTargetDesc/RISCVBaseInfo.h" #include "gtest/gtest.h" using namespace llvm; namespace { TEST(RISCVBaseInfo, CheckSameRatioLMUL) { // Smaller LMUL. EXPECT_EQ(RISCVII::LMUL_1, RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_2, 8)); EXPECT_EQ(RISCVII::LMUL_F2, RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_1, 8)); // Smaller fractional LMUL. EXPECT_EQ(RISCVII::LMUL_F8, RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_F4, 8)); // Bigger LMUL. EXPECT_EQ(RISCVII::LMUL_2, RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_1, 16)); EXPECT_EQ(RISCVII::LMUL_1, RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16)); // Bigger fractional LMUL. EXPECT_EQ(RISCVII::LMUL_F2, RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16)); } } // namespace