Commit 42fb60e1 authored by Tom Stellard's avatar Tom Stellard
Browse files

R600/SI: Spill VGPRs to scratch space for compute shaders 

llvm-svn: 225988
parent d657321a

llvm/lib/Target/R600/AMDGPU.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ FunctionPass *createSIFixSGPRCopiesPass(TargetMachine &tm); 
FunctionPass *createSIFixSGPRLiveRangesPass();

FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);

FunctionPass *createSIInsertWaits(TargetMachine &tm);

FunctionPass *createSIPrepareScratchRegs();



void initializeSIFoldOperandsPass(PassRegistry &);

extern char &SIFoldOperandsID;

llvm/lib/Target/R600/AMDGPUTargetMachine.cpp

+1 −0
Original line number Diff line number Diff line
@@ -189,6 +189,7 @@ void AMDGPUPassConfig::addPostRegAlloc() { 
  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();



  if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {

    addPass(createSIPrepareScratchRegs(), false);

    addPass(createSIShrinkInstructionsPass(), false);

  }

}

llvm/lib/Target/R600/CMakeLists.txt

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ add_llvm_target(R600CodeGen 
  SILowerControlFlow.cpp

  SILowerI1Copies.cpp

  SIMachineFunctionInfo.cpp

  SIPrepareScratchRegs.cpp

  SIRegisterInfo.cpp

  SIShrinkInstructions.cpp

  SITypeRewriter.cpp

llvm/lib/Target/R600/SIInstrInfo.cpp

+17 −9
Original line number Diff line number Diff line
@@ -433,13 +433,9 @@ unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { 
static bool shouldTryToSpillVGPRs(MachineFunction *MF) {



  SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();

  const TargetMachine &TM = MF->getTarget();



  // FIXME: Even though it can cause problems, we need to enable

  // spilling at -O0, since the fast register allocator always

  // spills registers that are live at the end of blocks.

  return MFI->getShaderType() == ShaderType::COMPUTE &&

         TM.getOptLevel() == CodeGenOpt::None;

  // FIXME: Implement spilling for other shader types.

  return MFI->getShaderType() == ShaderType::COMPUTE;



}
@@ -450,6 +446,7 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 
                                      const TargetRegisterClass *RC,

                                      const TargetRegisterInfo *TRI) const {

  MachineFunction *MF = MBB.getParent();

  SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();

  MachineFrameInfo *FrameInfo = MF->getFrameInfo();

  DebugLoc DL = MBB.findDebugLoc(MI);

  int Opcode = -1;
@@ -466,6 +463,8 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 
      case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;

    }

  } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {

    MFI->setHasSpilledVGPRs();



    switch(RC->getSize() * 8) {

      case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;

      case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
@@ -480,7 +479,11 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 
    FrameInfo->setObjectAlignment(FrameIndex, 4);

    BuildMI(MBB, MI, DL, get(Opcode))

            .addReg(SrcReg)

            .addFrameIndex(FrameIndex);

            .addFrameIndex(FrameIndex)

            // Place-holder registers, these will be filled in by

            // SIPrepareScratchRegs.

            .addReg(AMDGPU::SGPR0_SGPR1, RegState::Undef)

            .addReg(AMDGPU::SGPR0, RegState::Undef);

  } else {

    LLVMContext &Ctx = MF->getFunction()->getContext();

    Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
@@ -522,7 +525,12 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 
  if (Opcode != -1) {

    FrameInfo->setObjectAlignment(FrameIndex, 4);

    BuildMI(MBB, MI, DL, get(Opcode), DestReg)

            .addFrameIndex(FrameIndex);

            .addFrameIndex(FrameIndex)

            // Place-holder registers, these will be filled in by

            // SIPrepareScratchRegs.

            .addReg(AMDGPU::SGPR0_SGPR1, RegState::Undef)

            .addReg(AMDGPU::SGPR0, RegState::Undef);



  } else {

    LLVMContext &Ctx = MF->getFunction()->getContext();

    Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
@@ -553,7 +561,7 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB, 
    MachineBasicBlock::iterator Insert = Entry.front();

    DebugLoc DL = Insert->getDebugLoc();



    TIDReg = RI.findUnusedVGPR(MF->getRegInfo());

    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);

    if (TIDReg == AMDGPU::NoRegister)

      return TIDReg;

llvm/lib/Target/R600/SIInstrInfo.td

+2 −0
Original line number Diff line number Diff line
@@ -1763,6 +1763,7 @@ multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass, 
multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,

                          ValueType store_vt, SDPatternOperator st> {



  let mayLoad = 0, mayStore = 1 in {

  let addr64 = 0 in {



    def "" : MUBUF_si <
@@ -1820,6 +1821,7 @@ multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass 
      let tfe = 0;

      let soffset = 128; // ZERO

   }

   } // End mayLoad = 0, mayStore = 1

}



class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :