Commit 422dfea5 authored by Kazushi (Jam) Marukawa's avatar Kazushi (Jam) Marukawa Committed by Simon Moll
Browse files

[VE] enable unaligned load/store isel 

Summary: Enable unaligned load/store isel for iN and fp32/64 and tests.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D73448
parent 879c825c

llvm/lib/Target/VE/VEISelLowering.cpp

+21 −0
Original line number Diff line number Diff line
@@ -206,6 +206,27 @@ bool VETargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, 
  return VT == MVT::f32 || VT == MVT::f64;

}



/// Determine if the target supports unaligned memory accesses.

///

/// This function returns true if the target allows unaligned memory accesses

/// of the specified type in the given address space. If true, it also returns

/// whether the unaligned memory access is "fast" in the last argument by

/// reference. This is used, for example, in situations where an array

/// copy/move/set is converted to a sequence of store operations. Its use

/// helps to ensure that such replacements don't generate code that causes an

/// alignment error (trap) on the target machine.

bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,

                                                      unsigned AddrSpace,

                                                      unsigned Align,

                                                      MachineMemOperand::Flags,

                                                      bool *Fast) const {

  if (Fast) {

    // It's fast anytime on VE

    *Fast = true;

  }

  return true;

}



VETargetLowering::VETargetLowering(const TargetMachine &TM,

                                   const VESubtarget &STI)

    : TargetLowering(TM), Subtarget(&STI) {

llvm/lib/Target/VE/VEISelLowering.h

+5 −0
Original line number Diff line number Diff line
@@ -77,6 +77,11 @@ public: 


  bool isFPImmLegal(const APFloat &Imm, EVT VT,

                    bool ForCodeSize) const override;

  /// Returns true if the target allows unaligned memory accesses of the

  /// specified type.

  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,

                                      MachineMemOperand::Flags Flags,

                                      bool *Fast) const override;

};

} // namespace llvm

llvm/test/CodeGen/VE/load-align1.ll

0 → 100644
+153 −0
Original line number Diff line number Diff line 
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s



@vi8 = common dso_local local_unnamed_addr global i8 0, align 1

@vi16 = common dso_local local_unnamed_addr global i16 0, align 1

@vi32 = common dso_local local_unnamed_addr global i32 0, align 1

@vi64 = common dso_local local_unnamed_addr global i64 0, align 1

@vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 1

@vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 1



; Function Attrs: norecurse nounwind readonly

define double @loadf64stk() {

; CHECK-LABEL: loadf64stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld %s0, 184(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca double, align 1

  %1 = load double, double* %addr, align 1

  ret double %1

}



; Function Attrs: norecurse nounwind readonly

define float @loadf32stk() {

; CHECK-LABEL: loadf32stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ldu %s0, 188(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca float, align 1

  %1 = load float, float* %addr, align 1

  ret float %1

}



; Function Attrs: norecurse nounwind readonly

define i64 @loadi64stk() {

; CHECK-LABEL: loadi64stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld %s0, 184(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i64, align 1

  %1 = load i64, i64* %addr, align 1

  ret i64 %1

}



; Function Attrs: norecurse nounwind readonly

define i32 @loadi32stk() {

; CHECK-LABEL: loadi32stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ldl.sx %s0, 188(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i32, align 1

  %1 = load i32, i32* %addr, align 1

  ret i32 %1

}



; Function Attrs: norecurse nounwind readonly

define i16 @loadi16stk() {

; CHECK-LABEL: loadi16stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld2b.zx %s0, 190(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i16, align 1

  %1 = load i16, i16* %addr, align 1

  ret i16 %1

}



; Function Attrs: norecurse nounwind readonly

define i8 @loadi8stk() {

; CHECK-LABEL: loadi8stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld1b.zx %s0, 191(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i8, align 1

  %1 = load i8, i8* %addr, align 1

  ret i8 %1

}



; Function Attrs: norecurse nounwind readonly

define double @loadf64com() {

; CHECK-LABEL: loadf64com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vf64@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vf64@hi(%s0)

; CHECK-NEXT:    ld %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load double, double* @vf64, align 1

  ret double %1

}



; Function Attrs: norecurse nounwind readonly

define float @loadf32com() {

; CHECK-LABEL: loadf32com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vf32@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vf32@hi(%s0)

; CHECK-NEXT:    ldu %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load float, float* @vf32, align 1

  ret float %1

}



; Function Attrs: norecurse nounwind readonly

define i64 @loadi64com() {

; CHECK-LABEL: loadi64com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi64@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi64@hi(%s0)

; CHECK-NEXT:    ld %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i64, i64* @vi64, align 1

  ret i64 %1

}



; Function Attrs: norecurse nounwind readonly

define i32 @loadi32com() {

; CHECK-LABEL: loadi32com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi32@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi32@hi(%s0)

; CHECK-NEXT:    ldl.sx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i32, i32* @vi32, align 1

  ret i32 %1

}



; Function Attrs: norecurse nounwind readonly

define i16 @loadi16com() {

; CHECK-LABEL: loadi16com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi16@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi16@hi(%s0)

; CHECK-NEXT:    ld2b.zx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i16, i16* @vi16, align 1

  ret i16 %1

}



; Function Attrs: norecurse nounwind readonly

define i8 @loadi8com() {

; CHECK-LABEL: loadi8com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi8@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi8@hi(%s0)

; CHECK-NEXT:    ld1b.zx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i8, i8* @vi8, align 1

  ret i8 %1

}

llvm/test/CodeGen/VE/load-align2.ll

0 → 100644
+153 −0
Original line number Diff line number Diff line 
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s



@vi8 = common dso_local local_unnamed_addr global i8 0, align 2

@vi16 = common dso_local local_unnamed_addr global i16 0, align 2

@vi32 = common dso_local local_unnamed_addr global i32 0, align 2

@vi64 = common dso_local local_unnamed_addr global i64 0, align 2

@vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 2

@vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 2



; Function Attrs: norecurse nounwind readonly

define double @loadf64stk() {

; CHECK-LABEL: loadf64stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld %s0, 184(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca double, align 2

  %1 = load double, double* %addr, align 2

  ret double %1

}



; Function Attrs: norecurse nounwind readonly

define float @loadf32stk() {

; CHECK-LABEL: loadf32stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ldu %s0, 188(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca float, align 2

  %1 = load float, float* %addr, align 2

  ret float %1

}



; Function Attrs: norecurse nounwind readonly

define i64 @loadi64stk() {

; CHECK-LABEL: loadi64stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld %s0, 184(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i64, align 2

  %1 = load i64, i64* %addr, align 2

  ret i64 %1

}



; Function Attrs: norecurse nounwind readonly

define i32 @loadi32stk() {

; CHECK-LABEL: loadi32stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ldl.sx %s0, 188(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i32, align 2

  %1 = load i32, i32* %addr, align 2

  ret i32 %1

}



; Function Attrs: norecurse nounwind readonly

define i16 @loadi16stk() {

; CHECK-LABEL: loadi16stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld2b.zx %s0, 190(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i16, align 2

  %1 = load i16, i16* %addr, align 2

  ret i16 %1

}



; Function Attrs: norecurse nounwind readonly

define i8 @loadi8stk() {

; CHECK-LABEL: loadi8stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld1b.zx %s0, 190(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i8, align 2

  %1 = load i8, i8* %addr, align 2

  ret i8 %1

}



; Function Attrs: norecurse nounwind readonly

define double @loadf64com() {

; CHECK-LABEL: loadf64com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vf64@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vf64@hi(%s0)

; CHECK-NEXT:    ld %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load double, double* @vf64, align 2

  ret double %1

}



; Function Attrs: norecurse nounwind readonly

define float @loadf32com() {

; CHECK-LABEL: loadf32com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vf32@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vf32@hi(%s0)

; CHECK-NEXT:    ldu %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load float, float* @vf32, align 2

  ret float %1

}



; Function Attrs: norecurse nounwind readonly

define i64 @loadi64com() {

; CHECK-LABEL: loadi64com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi64@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi64@hi(%s0)

; CHECK-NEXT:    ld %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i64, i64* @vi64, align 2

  ret i64 %1

}



; Function Attrs: norecurse nounwind readonly

define i32 @loadi32com() {

; CHECK-LABEL: loadi32com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi32@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi32@hi(%s0)

; CHECK-NEXT:    ldl.sx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i32, i32* @vi32, align 2

  ret i32 %1

}



; Function Attrs: norecurse nounwind readonly

define i16 @loadi16com() {

; CHECK-LABEL: loadi16com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi16@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi16@hi(%s0)

; CHECK-NEXT:    ld2b.zx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i16, i16* @vi16, align 2

  ret i16 %1

}



; Function Attrs: norecurse nounwind readonly

define i8 @loadi8com() {

; CHECK-LABEL: loadi8com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi8@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi8@hi(%s0)

; CHECK-NEXT:    ld1b.zx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i8, i8* @vi8, align 2

  ret i8 %1

}

llvm/test/CodeGen/VE/load-align4.ll

0 → 100644
+153 −0
Original line number Diff line number Diff line 
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s



@vi8 = common dso_local local_unnamed_addr global i8 0, align 4

@vi16 = common dso_local local_unnamed_addr global i16 0, align 4

@vi32 = common dso_local local_unnamed_addr global i32 0, align 4

@vi64 = common dso_local local_unnamed_addr global i64 0, align 4

@vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 4

@vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 4



; Function Attrs: norecurse nounwind readonly

define double @loadf64stk() {

; CHECK-LABEL: loadf64stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld %s0, 184(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca double, align 4

  %1 = load double, double* %addr, align 4

  ret double %1

}



; Function Attrs: norecurse nounwind readonly

define float @loadf32stk() {

; CHECK-LABEL: loadf32stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ldu %s0, 188(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca float, align 4

  %1 = load float, float* %addr, align 4

  ret float %1

}



; Function Attrs: norecurse nounwind readonly

define i64 @loadi64stk() {

; CHECK-LABEL: loadi64stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld %s0, 184(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i64, align 4

  %1 = load i64, i64* %addr, align 4

  ret i64 %1

}



; Function Attrs: norecurse nounwind readonly

define i32 @loadi32stk() {

; CHECK-LABEL: loadi32stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ldl.sx %s0, 188(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i32, align 4

  %1 = load i32, i32* %addr, align 4

  ret i32 %1

}



; Function Attrs: norecurse nounwind readonly

define i16 @loadi16stk() {

; CHECK-LABEL: loadi16stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld2b.zx %s0, 188(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i16, align 4

  %1 = load i16, i16* %addr, align 4

  ret i16 %1

}



; Function Attrs: norecurse nounwind readonly

define i8 @loadi8stk() {

; CHECK-LABEL: loadi8stk:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    ld1b.zx %s0, 188(,%s11)

; CHECK-NEXT:    or %s11, 0, %s9

  %addr = alloca i8, align 4

  %1 = load i8, i8* %addr, align 4

  ret i8 %1

}



; Function Attrs: norecurse nounwind readonly

define double @loadf64com() {

; CHECK-LABEL: loadf64com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vf64@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vf64@hi(%s0)

; CHECK-NEXT:    ld %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load double, double* @vf64, align 4

  ret double %1

}



; Function Attrs: norecurse nounwind readonly

define float @loadf32com() {

; CHECK-LABEL: loadf32com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vf32@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vf32@hi(%s0)

; CHECK-NEXT:    ldu %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load float, float* @vf32, align 4

  ret float %1

}



; Function Attrs: norecurse nounwind readonly

define i64 @loadi64com() {

; CHECK-LABEL: loadi64com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi64@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi64@hi(%s0)

; CHECK-NEXT:    ld %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i64, i64* @vi64, align 4

  ret i64 %1

}



; Function Attrs: norecurse nounwind readonly

define i32 @loadi32com() {

; CHECK-LABEL: loadi32com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi32@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi32@hi(%s0)

; CHECK-NEXT:    ldl.sx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i32, i32* @vi32, align 4

  ret i32 %1

}



; Function Attrs: norecurse nounwind readonly

define i16 @loadi16com() {

; CHECK-LABEL: loadi16com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi16@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi16@hi(%s0)

; CHECK-NEXT:    ld2b.zx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i16, i16* @vi16, align 4

  ret i16 %1

}



; Function Attrs: norecurse nounwind readonly

define i8 @loadi8com() {

; CHECK-LABEL: loadi8com:

; CHECK:       .LBB{{[0-9]+}}_2:

; CHECK-NEXT:    lea %s0, vi8@lo

; CHECK-NEXT:    and %s0, %s0, (32)0

; CHECK-NEXT:    lea.sl %s0, vi8@hi(%s0)

; CHECK-NEXT:    ld1b.zx %s0, (,%s0)

; CHECK-NEXT:    or %s11, 0, %s9

  %1 = load i8, i8* @vi8, align 4

  ret i8 %1

}