Commit 3f910512 authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r368572: 

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r368572 | lenary | 2019-08-12 15:51:00 +0200 (Mon, 12 Aug 2019) | 18 lines

[RISCV] Fix ICE in isDesirableToCommuteWithShift

Summary:
Ana Pazos reported a bug where we were not checking that an APInt would
fit into 64-bits before calling `getSExtValue()`. This caused asserts when
compiling large constants, such as i128s, as happens when compiling compiler-rt.

This patch adds a testcase and makes the callback less error-prone.

Reviewers: apazos, asb, luismarques

Reviewed By: luismarques

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66081
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llvm-svn: 368674
parent 97e6d088

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+4 −2
Original line number Diff line number Diff line
@@ -1007,12 +1007,14 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift( 
      // We can materialise `c1 << c2` into an add immediate, so it's "free",

      // and the combine should happen, to potentially allow further combines

      // later.

      if (isLegalAddImmediate(ShiftedC1Int.getSExtValue()))

      if (ShiftedC1Int.getMinSignedBits() <= 64 &&

          isLegalAddImmediate(ShiftedC1Int.getSExtValue()))

        return true;



      // We can materialise `c1` in an add immediate, so it's "free", and the

      // combine should be prevented.

      if (isLegalAddImmediate(C1Int.getSExtValue()))

      if (C1Int.getMinSignedBits() <= 64 &&

          isLegalAddImmediate(C1Int.getSExtValue()))

        return false;



      // Neither constant will fit into an immediate, so find materialisation

llvm/test/CodeGen/RISCV/add-before-shl.ll

+40 −0
Original line number Diff line number Diff line
@@ -91,3 +91,43 @@ define signext i24 @add_non_machine_type(i24 signext %a) nounwind { 
  %2 = shl i24 %1, 12

  ret i24 %2

}



define i128 @add_wide_operand(i128 %a) nounwind {

; RV32I-LABEL: add_wide_operand:

; RV32I:       # %bb.0:

; RV32I-NEXT:    lw a2, 0(a1)

; RV32I-NEXT:    srli a3, a2, 29

; RV32I-NEXT:    lw a4, 4(a1)

; RV32I-NEXT:    slli a5, a4, 3

; RV32I-NEXT:    or a6, a5, a3

; RV32I-NEXT:    srli a4, a4, 29

; RV32I-NEXT:    lw a5, 8(a1)

; RV32I-NEXT:    slli a3, a5, 3

; RV32I-NEXT:    or a3, a3, a4

; RV32I-NEXT:    slli a2, a2, 3

; RV32I-NEXT:    sw a2, 0(a0)

; RV32I-NEXT:    sw a3, 8(a0)

; RV32I-NEXT:    sw a6, 4(a0)

; RV32I-NEXT:    srli a2, a5, 29

; RV32I-NEXT:    lw a1, 12(a1)

; RV32I-NEXT:    slli a1, a1, 3

; RV32I-NEXT:    or a1, a1, a2

; RV32I-NEXT:    lui a2, 128

; RV32I-NEXT:    add a1, a1, a2

; RV32I-NEXT:    sw a1, 12(a0)

; RV32I-NEXT:    ret

;

; RV64I-LABEL: add_wide_operand:

; RV64I:       # %bb.0:

; RV64I-NEXT:    slli a1, a1, 3

; RV64I-NEXT:    srli a2, a0, 61

; RV64I-NEXT:    or a1, a1, a2

; RV64I-NEXT:    addi a2, zero, 1

; RV64I-NEXT:    slli a2, a2, 51

; RV64I-NEXT:    add a1, a1, a2

; RV64I-NEXT:    slli a0, a0, 3

; RV64I-NEXT:    ret

  %1 = add i128 %a, 5192296858534827628530496329220096

  %2 = shl i128 %1, 3

  ret i128 %2

}