Commit 3c3d6350 authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r281479: 

------------------------------------------------------------------------
r281479 | nemanja.i.ibm | 2016-09-14 07:19:09 -0700 (Wed, 14 Sep 2016) | 9 lines

Fix code-gen crash on Power9 for insert_vector_elt with variable index (PR30189)

This patch corresponds to review:
https://reviews.llvm.org/D24021

In the initial implementation of this instruction, I forgot to account for
variable indices. This patch fixes PR30189 and should probably be merged into
3.9.1 (I'll open a bug according to the new instructions).

------------------------------------------------------------------------

llvm-svn: 287809
parent fa51fdfc

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+15 −2
Original line number Diff line number Diff line
@@ -665,9 +665,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, 
      addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);

      addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);

    }



    if (Subtarget.hasP9Vector()) {

      setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);

      setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Legal);

      setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);

      setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);

    }

  }
@@ -7846,6 +7847,17 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 
  return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo());

}



SDValue PPCTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,

                                                  SelectionDAG &DAG) const {

  assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&

         "Should only be called for ISD::INSERT_VECTOR_ELT");

  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(2));

  // We have legal lowering for constant indices but not for variable ones.

  if (C)

    return Op;

  return SDValue();

}



SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,

                                                   SelectionDAG &DAG) const {

  SDLoc dl(Op);
@@ -8248,6 +8260,7 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 
  case ISD::SCALAR_TO_VECTOR:   return LowerSCALAR_TO_VECTOR(Op, DAG);

  case ISD::SIGN_EXTEND_INREG:  return LowerSIGN_EXTEND_INREG(Op, DAG);

  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);

  case ISD::INSERT_VECTOR_ELT:  return LowerINSERT_VECTOR_ELT(Op, DAG);

  case ISD::MUL:                return LowerMUL(Op, DAG);



  // For counter-based loop handling.

llvm/lib/Target/PowerPC/PPCISelLowering.h

+1 −0
Original line number Diff line number Diff line
@@ -824,6 +824,7 @@ namespace llvm { 
    SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;

    SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;

    SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;

    SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;

    SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;

    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;

    SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;

llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll

+22 −0
Original line number Diff line number Diff line
@@ -968,3 +968,25 @@ entry: 
  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>

  ret <4 x float> %vecins

}

define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {

entry:

; CHECK-LABEL: insertVarF

; CHECK: stxsspx 1,

; CHECK: lxvd2x

; CHECK-BE-LABEL: insertVarF

; CHECK-BE: stxsspx 1,

; CHECK-BE: lxvw4x

  %vecins = insertelement <4 x float> %a, float %f, i32 %el

  ret <4 x float> %vecins

}

define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {

entry:

; CHECK-LABEL: insertVarI

; CHECK: stwx

; CHECK: lxvd2x

; CHECK-BE-LABEL: insertVarI

; CHECK-BE: stwx

; CHECK-BE: lxvw4x

  %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el

  ret <4 x i32> %vecins

}