Commit 3bc2860e authored by Zakk Chen's avatar Zakk Chen
Browse files

Revert "[RISCV] Support ABI checking with per function target-features" 

This reverts commit 109e4d12.
parent eb82226f

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

+0 −12
Original line number Diff line number Diff line
@@ -194,18 +194,6 @@ public: 
    Parser.addAliasForDirective(".word", ".4byte");

    Parser.addAliasForDirective(".dword", ".8byte");

    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));



    if (Options.ABIName.back() == 'f' &&

        !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) {

      errs() << "Hard-float 'f' ABI can't be used for a target that "

                "doesn't support the F instruction set extension (ignoring "

                "target-abi)\n";

    } else if (Options.ABIName.back() == 'd' &&

               !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) {

      errs() << "Hard-float 'd' ABI can't be used for a target that "

                "doesn't support the D instruction set extension (ignoring "

                "target-abi)\n";

    }

  }

};

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+0 −14
Original line number Diff line number Diff line
@@ -51,20 +51,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, 
  RISCVABI::ABI ABI = Subtarget.getTargetABI();

  assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");



  if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&

      !Subtarget.hasStdExtF()) {

    errs() << "Hard-float 'f' ABI can't be used for a target that "

                "doesn't support the F instruction set extension (ignoring "

                          "target-abi)\n";

    ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;

  } else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) &&

             !Subtarget.hasStdExtD()) {

    errs() << "Hard-float 'd' ABI can't be used for a target that "

              "doesn't support the D instruction set extension (ignoring "

              "target-abi)\n";

    ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;

  }



  switch (ABI) {

  default:

    report_fatal_error("Don't know how to lower this ABI");

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

+10 −1
Original line number Diff line number Diff line
@@ -37,8 +37,17 @@ ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, 
    errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "

              "target-abi)\n";

    TargetABI = ABI_Unknown;

  } else if (ABIName.endswith("f") && !FeatureBits[RISCV::FeatureStdExtF]) {

    errs() << "Hard-float 'f' ABI can't be used for a target that "

              "doesn't support the F instruction set extension (ignoring "

              "target-abi)\n";

    TargetABI = ABI_Unknown;

  } else if (ABIName.endswith("d") && !FeatureBits[RISCV::FeatureStdExtD]) {

    errs() << "Hard-float 'd' ABI can't be used for a target that "

              "doesn't support the D instruction set extension (ignoring "

              "target-abi)\n";

    TargetABI = ABI_Unknown;

  } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {

    // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser

    errs()

        << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";

    TargetABI = ABI_Unknown;

llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll

+3 −8
Original line number Diff line number Diff line
@@ -2,17 +2,12 @@ 
; RUN:   | FileCheck -check-prefix=RV32IF-ILP32 %s

; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \

; RUN:   | FileCheck -check-prefix=RV32IF-ILP32F %s

; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \

; RUN:   | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s



; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension



; RV32IF-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)



define float @foo(i32 %a) nounwind #0 {

; RV32IF-ILP32: fcvt.s.w  ft0, a0

; RV32IF-ILP32-NEXT: fmv.x.w a0, ft0

; RV32IF-ILP32F: fcvt.s.w fa0, a0

; RV32IF-ILP32F-NEXT: ret

; RV32IF-ILP32: # %bb.0:

; RV32IF-ILP32-NEXT: fcvt.s.w  ft0, a0

  %conv = sitofp i32 %a to float

  ret float %conv

}