Commit 3a906a9f authored by Kazushi (Jam) Marukawa's avatar Kazushi (Jam) Marukawa Committed by Simon Moll
Browse files

[VE] i<N> and fp32/64 arguments, return values and constants 

Summary:
Support for i<N> and fp32/64 arguments (in register), return values
and constants along with tests.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D73092
parent c9a39a89

llvm/lib/Target/VE/VECallingConv.td

+28 −2
Original line number Diff line number Diff line
@@ -17,14 +17,40 @@ 
def CC_VE : CallingConv<[

  // All arguments get passed in generic registers if there is space.



  // Promote i1/i8/i16 arguments to i32.

  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,



  // bool, char, int, enum, long --> generic integer 32 bit registers

  CCIfType<[i32], CCAssignToRegWithShadow<

    [SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7],

    [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,



  // float --> generic floating point 32 bit registers

  CCIfType<[f32], CCAssignToRegWithShadow<

    [SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7],

    [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,



  // long long/double --> generic 64 bit registers

  CCIfType<[i64],

  CCIfType<[i64, f64],

           CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,

]>;



def RetCC_VE : CallingConv<[

  // Promote i1/i8/i16 arguments to i32.

  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,



  // bool, char, int, enum, long --> generic integer 32 bit registers

  CCIfType<[i32], CCAssignToRegWithShadow<

    [SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7],

    [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,



  // float --> generic floating point 32 bit registers

  CCIfType<[f32], CCAssignToRegWithShadow<

    [SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7],

    [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,



  // long long/double --> generic 64 bit registers

  CCIfType<[i64],

  CCIfType<[i64, f64],

           CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,

]>;

llvm/lib/Target/VE/VEISelLowering.cpp

+17 −2
Original line number Diff line number Diff line
@@ -89,6 +89,8 @@ VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 
      llvm_unreachable("Unknown loc info!");

    }



    assert(!VA.needsCustom() && "Unexpected custom lowering");



    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);



    // Guarantee that all emitted copies are stuck together with flags.
@@ -136,8 +138,10 @@ SDValue VETargetLowering::LowerFormalArguments( 
          MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));

      SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());



      assert((VA.getValVT() == MVT::i64) &&

             "TODO implement other argument types than i64");

      // Get the high bits for i32 struct elements.

      if (VA.getValVT() == MVT::i32 && VA.needsCustom())

        Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,

                          DAG.getConstant(32, DL, MVT::i32));



      // The caller promoted the argument, so insert an Assert?ext SDNode so we

      // won't promote the value again in this function.
@@ -193,6 +197,14 @@ Register VETargetLowering::getRegisterByName(const char *RegName, LLT VT, 
// TargetLowering Implementation

//===----------------------------------------------------------------------===//



/// isFPImmLegal - Returns true if the target can instruction select the

/// specified FP immediate natively. If false, the legalizer will

/// materialize the FP immediate as a load from a constant pool.

bool VETargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,

                                    bool ForCodeSize) const {

  return VT == MVT::f32 || VT == MVT::f64;

}



VETargetLowering::VETargetLowering(const TargetMachine &TM,

                                   const VESubtarget &STI)

    : TargetLowering(TM), Subtarget(&STI) {
@@ -205,7 +217,10 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM, 
  setBooleanVectorContents(ZeroOrOneBooleanContent);



  // Set up the register classes.

  addRegisterClass(MVT::i32, &VE::I32RegClass);

  addRegisterClass(MVT::i64, &VE::I64RegClass);

  addRegisterClass(MVT::f32, &VE::F32RegClass);

  addRegisterClass(MVT::f64, &VE::I64RegClass);



  setStackPointerRegisterToSaveRestore(VE::SX11);

llvm/lib/Target/VE/VEISelLowering.h

+6 −0
Original line number Diff line number Diff line
@@ -34,6 +34,9 @@ public: 
  VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);



  const char *getTargetNodeName(unsigned Opcode) const override;

  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {

    return MVT::i32;

  }



  Register getRegisterByName(const char *RegName, LLT VT,

                             const MachineFunction &MF) const override;
@@ -56,6 +59,9 @@ public: 
                      const SmallVectorImpl<ISD::OutputArg> &Outs,

                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,

                      SelectionDAG &DAG) const override;



  bool isFPImmLegal(const APFloat &Imm, EVT VT,

                    bool ForCodeSize) const override;

};

} // namespace llvm

llvm/lib/Target/VE/VEInstrFormats.td

+2 −2
Original line number Diff line number Diff line
@@ -44,8 +44,8 @@ class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]> 
  let Inst{63-32}  = imm32;

}



class RR<bits<8>opVal, dag outs, dag ins, string asmstr>

   : RM<opVal, outs, ins, asmstr> {

class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>

   : RM<opVal, outs, ins, asmstr, pattern> {

  bits<1> cw = 0;

  bits<1> cw2 = 0;

  bits<4> cfw = 0;

llvm/lib/Target/VE/VEInstrInfo.cpp

+7 −1
Original line number Diff line number Diff line
@@ -38,12 +38,18 @@ VEInstrInfo::VEInstrInfo(VESubtarget &ST) 
    : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI(),

      Subtarget(ST) {}



static bool IsAliasOfSX(Register Reg) {

  return VE::I8RegClass.contains(Reg) || VE::I16RegClass.contains(Reg) ||

         VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||

         VE::F32RegClass.contains(Reg);

}



void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,

                              MachineBasicBlock::iterator I, const DebugLoc &DL,

                              MCRegister DestReg, MCRegister SrcReg,

                              bool KillSrc) const {



  if (VE::I64RegClass.contains(SrcReg) && VE::I64RegClass.contains(DestReg)) {

  if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) {

    BuildMI(MBB, I, DL, get(VE::ORri), DestReg)

        .addReg(SrcReg, getKillRegState(KillSrc))

        .addImm(0);