Commit 36eedfcb authored by Justin Hibbits's avatar Justin Hibbits
Browse files

[PowerPC] Fix powerpcspe subtarget enablement in llvm backend 

Summary:
As currently written, -target powerpcspe will enable SPE regardless of
disabling the feature later on in the command line.  Instead, change
this to just set a default CPU to 'e500' instead of a generic CPU.

As part of this, add FeatureSPE to the e500 definition.

Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D72673
parent d18fbfc0

llvm/lib/Target/PowerPC/PPC.td

+1 −1
Original line number Diff line number Diff line
@@ -442,7 +442,7 @@ def : ProcessorModel<"g5", G5Model, 
def : ProcessorModel<"e500", PPCE500Model,

                  [DirectiveE500,

                   FeatureICBT, FeatureBookE,

                   FeatureISEL, FeatureMFTB]>;

                   FeatureISEL, FeatureMFTB, FeatureSPE]>;

def : ProcessorModel<"e500mc", PPCE500mcModel,

                  [DirectiveE500mc,

                   FeatureSTFIWX, FeatureICBT, FeatureBookE,

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

+2 −3
Original line number Diff line number Diff line
@@ -127,6 +127,8 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 
    // If cross-compiling with -march=ppc64le without -mcpu

    if (TargetTriple.getArch() == Triple::ppc64le)

      CPUName = "ppc64le";

    else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)

      CPUName = "e500";

    else

      CPUName = "generic";

  }
@@ -151,9 +153,6 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 
      TargetTriple.isMusl())

    SecurePlt = true;



  if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)

    HasSPE = true;



  if (HasSPE && IsPPC64)

    report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);

  if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))