Commit 364326ce authored by Matt Arsenault's avatar Matt Arsenault Committed by Matt Arsenault
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AMDGPU/GlobalISel: Add mem operand to s.buffer.load intrinsic 

Really the intrinsic definition is wrong, but work around this
here. The DAG lowering introduces an MMO. We have to introduce a new
operation to avoid the verifier complaining about the missing mayLoad.
parent 0a389c81

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

+27 −11
Original line number Diff line number Diff line
@@ -3204,22 +3204,38 @@ bool AMDGPULegalizerInfo::legalizeSBufferLoad( 
  Register Dst = MI.getOperand(0).getReg();

  LLT Ty = B.getMRI()->getType(Dst);

  unsigned Size = Ty.getSizeInBits();

  MachineFunction &MF = B.getMF();



  Observer.changingInstr(MI);



  // FIXME: We don't really need this intermediate instruction. The intrinsic

  // should be fixed to have a memory operand. Since it's readnone, we're not

  // allowed to add one.

  MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_LOAD));

  MI.RemoveOperand(1); // Remove intrinsic ID



  // FIXME: When intrinsic definition is fixed, this should have an MMO already.

  // TODO: Should this use datalayout alignment?

  const unsigned MemSize = (Size + 7) / 8;

  const unsigned MemAlign = 4;

  MachineMemOperand *MMO = MF.getMachineMemOperand(

    MachinePointerInfo(),

    MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |

    MachineMemOperand::MOInvariant, MemSize, MemAlign);

  MI.addMemOperand(MF, MMO);



  // There are no 96-bit result scalar loads, but widening to 128-bit should

  // always be legal. We may need to restore this to a 96-bit result if it turns

  // out this needs to be converted to a vector load during RegBankSelect.

  if (isPowerOf2_32(Size))

    return true;



  LegalizerHelper Helper(B.getMF(), *this, Observer, B);

  if (!isPowerOf2_32(Size)) {

    LegalizerHelper Helper(MF, *this, Observer, B);

    B.setInstr(MI);



  Observer.changingInstr(MI);



    if (Ty.isVector())

      Helper.moreElementsVectorDst(MI, getPow2VectorType(Ty), 0);

    else

      Helper.widenScalarDst(MI, getPow2ScalarType(Ty), 0);

  }



  Observer.changedInstr(MI);

  return true;

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

+20 −27
Original line number Diff line number Diff line
@@ -2293,13 +2293,12 @@ void AMDGPURegisterBankInfo::applyMappingImpl( 
    executeInWaterfallLoop(MI, MRI, {3, 6});

    return;

  }

  case AMDGPU::G_INTRINSIC: {

    switch (MI.getIntrinsicID()) {

    case Intrinsic::amdgcn_s_buffer_load: {

      // FIXME: Move to G_INTRINSIC_W_SIDE_EFFECTS

      executeInWaterfallLoop(MI, MRI, { 2, 3 });

  case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: {

    executeInWaterfallLoop(MI, MRI, { 1, 2 });

    return;

  }

  case AMDGPU::G_INTRINSIC: {

    switch (MI.getIntrinsicID()) {

    case Intrinsic::amdgcn_readlane: {

      substituteSimpleCopyRegs(OpdMapper, 2);
@@ -3183,6 +3182,22 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
    // initialized.

    break;

  }

  case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: {

    // Lie and claim everything is legal, even though some need to be

    // SGPRs. applyMapping will have to deal with it as a waterfall loop.

    OpdsMapping[1] = getSGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);

    OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);



    // We need to convert this to a MUBUF if either the resource of offset is

    // VGPR.

    unsigned RSrcBank = OpdsMapping[1]->BreakDown[0].RegBank->getID();

    unsigned OffsetBank = OpdsMapping[2]->BreakDown[0].RegBank->getID();

    unsigned ResultBank = regBankUnion(RSrcBank, OffsetBank);



    unsigned Size0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();

    OpdsMapping[0] = AMDGPU::getValueMapping(ResultBank, Size0);

    break;

  }

  case AMDGPU::G_INTRINSIC: {

    switch (MI.getIntrinsicID()) {

    default:
@@ -3267,28 +3282,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
      OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1);

      break;

    }

    case Intrinsic::amdgcn_s_buffer_load: {

      // FIXME: This should be moved to G_INTRINSIC_W_SIDE_EFFECTS

      Register RSrc = MI.getOperand(2).getReg();   // SGPR

      Register Offset = MI.getOperand(3).getReg(); // SGPR/imm



      unsigned Size0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();

      unsigned Size2 = MRI.getType(RSrc).getSizeInBits();

      unsigned Size3 = MRI.getType(Offset).getSizeInBits();



      unsigned RSrcBank = getRegBankID(RSrc, MRI, *TRI);

      unsigned OffsetBank = getRegBankID(Offset, MRI, *TRI);



      OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size0);

      OpdsMapping[1] = nullptr; // intrinsic id



      // Lie and claim everything is legal, even though some need to be

      // SGPRs. applyMapping will have to deal with it as a waterfall loop.

      OpdsMapping[2] = AMDGPU::getValueMapping(RSrcBank, Size2); // rsrc

      OpdsMapping[3] = AMDGPU::getValueMapping(OffsetBank, Size3);

      OpdsMapping[4] = nullptr;

      break;

    }

    case Intrinsic::amdgcn_div_scale: {

      unsigned Dst0Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();

      unsigned Dst1Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();

llvm/lib/Target/AMDGPU/SIInstructions.td

+11 −0
Original line number Diff line number Diff line
@@ -2270,3 +2270,14 @@ def G_AMDGPU_BUFFER_ATOMIC_CMPSWAP : AMDGPUGenericInstruction { 
  let mayLoad = 1;

  let mayStore = 1;

}



// Wrapper around llvm.amdgcn.s.buffer.load. This is mostly needed as

// a workaround for the intrinsic being defined as readnone, but

// really needs a memory operand.

def G_AMDGPU_S_BUFFER_LOAD : AMDGPUGenericInstruction {

  let OutOperandList = (outs type0:$dst);

  let InOperandList = (ins type1:$rsrc, type2:$offset, untyped_imm_0:$cachepolicy);

  let hasSideEffects = 0;

  let mayLoad = 1;

  let mayStore = 0;

}

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir

+32 −14
Original line number Diff line number Diff line
@@ -2,6 +2,24 @@ 
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s



---

name: s_buffer_load_s32

body:             |

  bb.0:

    liveins: $sgpr0_sgpr1_sgpr2_sgpr3



    ; GCN-LABEL: name: s_buffer_load_s32

    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 4)

    ; GCN: S_ENDPGM 0, implicit [[AMDGPU_S_BUFFER_LOAD]](s32)

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = G_CONSTANT i32 0

    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0

    S_ENDPGM 0, implicit %2



...



---

name: s_buffer_load_v3s32

body:             |
@@ -11,8 +29,8 @@ body: | 
    ; GCN-LABEL: name: s_buffer_load_v3s32

    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; GCN: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[INT]](<4 x s32>), 0

    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), 0

    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s32>)

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = G_CONSTANT i32 0
@@ -30,8 +48,8 @@ body: | 
    ; GCN-LABEL: name: s_buffer_load_v3p3

    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; GCN: [[INT:%[0-9]+]]:_(<4 x p3>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x p3>) = G_EXTRACT [[INT]](<4 x p3>), 0

    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x p3>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x p3>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<4 x p3>), 0

    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x p3>)

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = G_CONSTANT i32 0
@@ -49,8 +67,8 @@ body: | 
    ; GCN-LABEL: name: s_buffer_load_v6s16

    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; GCN: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<6 x s16>) = G_EXTRACT [[INT]](<8 x s16>), 0

    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<8 x s16>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<6 x s16>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<8 x s16>), 0

    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<6 x s16>)

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = G_CONSTANT i32 0
@@ -68,8 +86,8 @@ body: | 
    ; GCN-LABEL: name: s_buffer_load_v6s32

    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; GCN: [[INT:%[0-9]+]]:_(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<6 x s32>) = G_EXTRACT [[INT]](<8 x s32>), 0

    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 24, align 4)

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<6 x s32>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>), 0

    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<6 x s32>)

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = G_CONSTANT i32 0
@@ -87,8 +105,8 @@ body: | 
    ; GCN-LABEL: name: s_buffer_load_v3s64

    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; GCN: [[INT:%[0-9]+]]:_(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[INT]](<4 x s64>), 0

    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s64>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 24, align 4)

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<4 x s64>), 0

    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s64>)

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = G_CONSTANT i32 0
@@ -106,8 +124,8 @@ body: | 
    ; GCN-LABEL: name: s_buffer_load_v12s8

    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; GCN: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<12 x s8>) = G_EXTRACT [[INT]](<16 x s8>), 0

    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<16 x s8>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<12 x s8>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<16 x s8>), 0

    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<12 x s8>)

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = G_CONSTANT i32 0
@@ -125,8 +143,8 @@ body: | 
    ; GCN-LABEL: name: s_buffer_load_s96

    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; GCN: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[INT]](<4 x s32>), 0

    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)

    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), 0

    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s32>)

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = G_CONSTANT i32 0

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir

+15 −15
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s

# XUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s



---

name: buffer_load_ss
@@ -14,10 +14,10 @@ body: | 
    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4

    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

    ; CHECK: [[INT:%[0-9]+]]:sgpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[COPY1]](s32), 0

    ; CHECK: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[COPY1]](s32), 0

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = COPY $sgpr4

    %2:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0

    %2:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD %0, %1, 0



...
@@ -34,16 +34,16 @@ body: | 
    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0

    ; CHECK: [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF

    ; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

    ; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

    ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

    ; CHECK: .1:

    ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)

    ; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.0, %8, %bb.1

    ; CHECK: [[PHI1:%[0-9]+]]:sgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %2(<4 x s32>), %bb.1

    ; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %2(<4 x s32>), %bb.1

    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec

    ; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec

    ; CHECK: [[INT:%[0-9]+]]:sgpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[V_READFIRSTLANE_B32_]](s32), 0

    ; CHECK: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[V_READFIRSTLANE_B32_]](s32), 0

    ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec

    ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc

    ; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
@@ -53,7 +53,7 @@ body: | 
    ; CHECK: .3:

    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

    %1:_(s32) = COPY $vgpr0

    %2:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0

    %2:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD %0, %1, 0



...
@@ -70,14 +70,14 @@ body: | 
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3

    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0

    ; CHECK: [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF

    ; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

    ; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

    ; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)

    ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

    ; CHECK: .1:

    ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)

    ; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.0, %8, %bb.1

    ; CHECK: [[PHI1:%[0-9]+]]:sgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %2(<4 x s32>), %bb.1

    ; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %2(<4 x s32>), %bb.1

    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec

    ; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec

    ; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
@@ -88,7 +88,7 @@ body: | 
    ; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec

    ; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc

    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)

    ; CHECK: [[INT:%[0-9]+]]:sgpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32), 0

    ; CHECK: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32), 0

    ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec

    ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc

    ; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
@@ -98,7 +98,7 @@ body: | 
    ; CHECK: .3:

    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3

    %1:_(s32) = COPY $sgpr0

    %2:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0

    %2:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD %0, %1, 0



...
@@ -115,14 +115,14 @@ body: | 
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4

    ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr4

    ; CHECK: [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF

    ; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

    ; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

    ; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)

    ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

    ; CHECK: .1:

    ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)

    ; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.0, %8, %bb.1

    ; CHECK: [[PHI1:%[0-9]+]]:sgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %2(<4 x s32>), %bb.1

    ; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %2(<4 x s32>), %bb.1

    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec

    ; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec

    ; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
@@ -136,7 +136,7 @@ body: | 
    ; CHECK: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec

    ; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]](s32), [[COPY1]](s32), implicit $exec

    ; CHECK: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[S_AND_B64_]], implicit-def $scc

    ; CHECK: [[INT:%[0-9]+]]:sgpr(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[BUILD_VECTOR]](<4 x s32>), [[V_READFIRSTLANE_B32_4]](s32), 0

    ; CHECK: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[V_READFIRSTLANE_B32_4]](s32), 0

    ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec

    ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc

    ; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
@@ -146,6 +146,6 @@ body: | 
    ; CHECK: .3:

    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3

    %1:_(s32) = COPY $vgpr4

    %2:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0

    %2:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD %0, %1, 0



...