Commit 342257ea authored by Eugene Zelenko's avatar Eugene Zelenko
Browse files

[ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 

llvm-svn: 293578
parent 6f5f001f

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

+13 −8
Original line number Diff line number Diff line
@@ -17,16 +17,21 @@ 
#include "MCTargetDesc/ARMBaseInfo.h"

#include "llvm/ADT/DenseMap.h"

#include "llvm/ADT/SmallSet.h"

#include "llvm/CodeGen/MachineBasicBlock.h"

#include "llvm/CodeGen/MachineInstr.h"

#include "llvm/CodeGen/MachineInstrBuilder.h"

#include "llvm/Support/CodeGen.h"

#include "llvm/CodeGen/MachineOperand.h"

#include "llvm/Target/TargetInstrInfo.h"

#include <array>

#include <cstdint>



#define GET_INSTRINFO_HEADER

#include "ARMGenInstrInfo.inc"



namespace llvm {

  class ARMSubtarget;



class ARMBaseRegisterInfo;

class ARMSubtarget;



class ARMBaseInstrInfo : public ARMGenInstrInfo {

  const ARMSubtarget &Subtarget;
@@ -409,13 +414,13 @@ public: 
static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,

                                                    unsigned PredReg = 0) {

  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),

           MachineOperand::CreateReg(PredReg, 0)}};

           MachineOperand::CreateReg(PredReg, false)}};

}



/// Get the operand corresponding to the conditional code result. By default,

/// this is 0 (no register).

static inline MachineOperand condCodeOp(unsigned CCReg = 0) {

  return MachineOperand::CreateReg(CCReg, 0);

  return MachineOperand::CreateReg(CCReg, false);

}



/// Get the operand corresponding to the conditional code result for Thumb1.
@@ -522,6 +527,6 @@ bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 
                         unsigned FrameReg, int &Offset,

                         const ARMBaseInstrInfo &TII);



} // End llvm namespace

} // end namespace llvm



#endif
 
#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

+19 −13
Original line number Diff line number Diff line
@@ -11,32 +11,42 @@ 
//

//===----------------------------------------------------------------------===//



#include "ARMBaseRegisterInfo.h"

#include "ARM.h"

#include "ARMBaseInstrInfo.h"

#include "ARMBaseRegisterInfo.h"

#include "ARMFrameLowering.h"

#include "ARMMachineFunctionInfo.h"

#include "ARMSubtarget.h"

#include "MCTargetDesc/ARMAddressingModes.h"

#include "MCTargetDesc/ARMBaseInfo.h"

#include "llvm/ADT/BitVector.h"

#include "llvm/ADT/SmallVector.h"

#include "llvm/ADT/STLExtras.h"

#include "llvm/CodeGen/MachineBasicBlock.h"

#include "llvm/CodeGen/MachineConstantPool.h"

#include "llvm/CodeGen/MachineFrameInfo.h"

#include "llvm/CodeGen/MachineFunction.h"

#include "llvm/CodeGen/MachineInstr.h"

#include "llvm/CodeGen/MachineInstrBuilder.h"

#include "llvm/CodeGen/MachineOperand.h"

#include "llvm/CodeGen/MachineRegisterInfo.h"

#include "llvm/CodeGen/RegisterScavenging.h"

#include "llvm/CodeGen/VirtRegMap.h"

#include "llvm/IR/Attributes.h"

#include "llvm/IR/Constants.h"

#include "llvm/IR/DerivedTypes.h"

#include "llvm/IR/DebugLoc.h"

#include "llvm/IR/Function.h"

#include "llvm/IR/LLVMContext.h"

#include "llvm/IR/Type.h"

#include "llvm/MC/MCInstrDesc.h"

#include "llvm/Support/Debug.h"

#include "llvm/Support/ErrorHandling.h"

#include "llvm/Support/raw_ostream.h"

#include "llvm/Target/TargetFrameLowering.h"

#include "llvm/Target/TargetInstrInfo.h"

#include "llvm/Target/TargetMachine.h"

#include "llvm/Target/TargetOptions.h"

#include "llvm/Target/TargetRegisterInfo.h"

#include <cassert>

#include <utility>



#define DEBUG_TYPE "arm-register-info"
@@ -46,7 +56,7 @@ 
using namespace llvm;



ARMBaseRegisterInfo::ARMBaseRegisterInfo()

    : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}

    : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}



static unsigned getFramePointerReg(const ARMSubtarget &STI) {

  return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
@@ -140,7 +150,6 @@ ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) con 
    return CSR_FPRegs_RegMask;

}





const uint32_t *

ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,

                                                CallingConv::ID CC) const {
@@ -475,26 +484,23 @@ getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 
    Scale = 4;

    break;

  }

  case ARMII::AddrMode2: {

  case ARMII::AddrMode2:

    ImmIdx = Idx+2;

    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());

    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)

      InstrOffs = -InstrOffs;

    break;

  }

  case ARMII::AddrMode3: {

  case ARMII::AddrMode3:

    ImmIdx = Idx+2;

    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());

    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)

      InstrOffs = -InstrOffs;

    break;

  }

  case ARMII::AddrModeT1_s: {

  case ARMII::AddrModeT1_s:

    ImmIdx = Idx+1;

    InstrOffs = MI->getOperand(ImmIdx).getImm();

    Scale = 4;

    break;

  }

  default:

    llvm_unreachable("Unsupported addressing mode!");

  }

llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

+14 −3
Original line number Diff line number Diff line
@@ -15,24 +15,33 @@ 
#define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H



#include "MCTargetDesc/ARMBaseInfo.h"

#include "llvm/CodeGen/MachineBasicBlock.h"

#include "llvm/CodeGen/MachineInstr.h"

#include "llvm/IR/CallingConv.h"

#include "llvm/MC/MCRegisterInfo.h"

#include "llvm/Target/TargetRegisterInfo.h"

#include <cstdint>



#define GET_REGINFO_HEADER

#include "ARMGenRegisterInfo.inc"



namespace llvm {



/// Register allocation hints.

namespace ARMRI {



  enum {

    RegPairOdd  = 1,

    RegPairEven = 2

  };

}



} // end namespace ARMRI



/// isARMArea1Register - Returns true if the register is a low register (r0-r7)

/// or a stack/pc register that we should push/pop.

static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {

  using namespace ARM;



  switch (Reg) {

    case R0:  case R1:  case R2:  case R3:

    case R4:  case R5:  case R6:  case R7:
@@ -48,6 +57,7 @@ static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { 


static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {

  using namespace ARM;



  switch (Reg) {

    case R8: case R9: case R10: case R11: case R12:

      // iOS has this second area.
@@ -59,6 +69,7 @@ static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { 


static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {

  using namespace ARM;



  switch (Reg) {

    case D15: case D14: case D13: case D12:

    case D11: case D10: case D9:  case D8:
@@ -87,7 +98,7 @@ protected: 
  /// BasePtr - ARM physical register used as a base ptr in complex stack

  /// frames. I.e., when we need a 3rd base, not just SP and FP, due to

  /// variable size stack objects.

  unsigned BasePtr;

  unsigned BasePtr = ARM::R6;



  // Can be only subclassed.

  explicit ARMBaseRegisterInfo();
@@ -198,4 +209,4 @@ public: 


} // end namespace llvm



#endif
 
#endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H

llvm/lib/Target/ARM/ARMFastISel.cpp

+60 −29
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
//===----------------------------------------------------------------------===//



#include "ARM.h"

#include "ARMBaseInstrInfo.h"

#include "ARMBaseRegisterInfo.h"

#include "ARMCallingConv.h"

#include "ARMConstantPoolValue.h"
@@ -21,30 +22,61 @@ 
#include "ARMMachineFunctionInfo.h"

#include "ARMSubtarget.h"

#include "MCTargetDesc/ARMAddressingModes.h"

#include "MCTargetDesc/ARMBaseInfo.h"

#include "llvm/ADT/APFloat.h"

#include "llvm/ADT/APInt.h"

#include "llvm/ADT/DenseMap.h"

#include "llvm/ADT/SmallVector.h"

#include "llvm/ADT/STLExtras.h"

#include "llvm/CodeGen/CallingConvLower.h"

#include "llvm/CodeGen/FastISel.h"

#include "llvm/CodeGen/FunctionLoweringInfo.h"

#include "llvm/CodeGen/ISDOpcodes.h"

#include "llvm/CodeGen/MachineConstantPool.h"

#include "llvm/CodeGen/MachineFrameInfo.h"

#include "llvm/CodeGen/MachineInstr.h"

#include "llvm/CodeGen/MachineInstrBuilder.h"

#include "llvm/CodeGen/MachineMemOperand.h"

#include "llvm/CodeGen/MachineModuleInfo.h"

#include "llvm/CodeGen/MachineOperand.h"

#include "llvm/CodeGen/MachineRegisterInfo.h"

#include "llvm/CodeGen/MachineValueType.h"

#include "llvm/CodeGen/RuntimeLibcalls.h"

#include "llvm/CodeGen/ValueTypes.h"

#include "llvm/IR/Argument.h"

#include "llvm/IR/Attributes.h"

#include "llvm/IR/CallSite.h"

#include "llvm/IR/CallingConv.h"

#include "llvm/IR/Constant.h"

#include "llvm/IR/Constants.h"

#include "llvm/IR/DataLayout.h"

#include "llvm/IR/DerivedTypes.h"

#include "llvm/IR/Function.h"

#include "llvm/IR/GetElementPtrTypeIterator.h"

#include "llvm/IR/GlobalValue.h"

#include "llvm/IR/GlobalVariable.h"

#include "llvm/IR/InstrTypes.h"

#include "llvm/IR/Instruction.h"

#include "llvm/IR/Instructions.h"

#include "llvm/IR/IntrinsicInst.h"

#include "llvm/IR/Module.h"

#include "llvm/IR/Operator.h"

#include "llvm/IR/Type.h"

#include "llvm/IR/User.h"

#include "llvm/IR/Value.h"

#include "llvm/MC/MCInstrDesc.h"

#include "llvm/MC/MCRegisterInfo.h"

#include "llvm/Support/Casting.h"

#include "llvm/Support/Compiler.h"

#include "llvm/Support/ErrorHandling.h"

#include "llvm/Support/MathExtras.h"

#include "llvm/Target/TargetInstrInfo.h"

#include "llvm/Target/TargetLowering.h"

#include "llvm/Target/TargetMachine.h"

#include "llvm/Target/TargetOptions.h"

#include <cassert>

#include <cstdint>

#include <utility>



using namespace llvm;



namespace {
@@ -54,24 +86,22 @@ namespace { 
    enum {

      RegBase,

      FrameIndexBase

    } BaseType;

    } BaseType = RegBase;



    union {

      unsigned Reg;

      int FI;

    } Base;



    int Offset;

    int Offset = 0;



    // Innocuous defaults for our address.

    Address()

     : BaseType(RegBase), Offset(0) {

    Address() {

      Base.Reg = 0;

    }

  } Address;



class ARMFastISel final : public FastISel {



  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can

  /// make the right decision when generating code for different targets.

  const ARMSubtarget *Subtarget;
@@ -99,8 +129,9 @@ class ARMFastISel final : public FastISel { 
      Context = &funcInfo.Fn->getContext();

    }



    // Code from FastISel.cpp.

  private:

    // Code from FastISel.cpp.



    unsigned fastEmitInst_r(unsigned MachineInstOpcode,

                            const TargetRegisterClass *RC,

                            unsigned Op0, bool Op0IsKill);
@@ -117,18 +148,18 @@ class ARMFastISel final : public FastISel { 
                            uint64_t Imm);



    // Backend specific FastISel code.

  private:



    bool fastSelectInstruction(const Instruction *I) override;

    unsigned fastMaterializeConstant(const Constant *C) override;

    unsigned fastMaterializeAlloca(const AllocaInst *AI) override;

    bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,

                             const LoadInst *LI) override;

    bool fastLowerArguments() override;

  private:



  #include "ARMGenFastISel.inc"



    // Instruction selection routines.

  private:



    bool SelectLoad(const Instruction *I);

    bool SelectStore(const Instruction *I);

    bool SelectBranch(const Instruction *I);
@@ -151,7 +182,7 @@ class ARMFastISel final : public FastISel { 
    bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);



    // Utility routines.

  private:



    bool isPositionIndependent() const;

    bool isTypeLegal(Type *Ty, MVT &VT);

    bool isLoadTypeLegal(Type *Ty, MVT &VT);
@@ -179,7 +210,7 @@ class ARMFastISel final : public FastISel { 
    const TargetLowering *getTargetLowering() { return &TLI; }



    // Call handling routines.

  private:



    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,

                                  bool Return,

                                  bool isVarArg);
@@ -198,7 +229,7 @@ class ARMFastISel final : public FastISel { 
    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);



    // OptionalDef handling routines.

  private:



    bool isARMNEONPred(const MachineInstr *MI);

    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);

    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
@@ -430,7 +461,6 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { 
}



unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {



  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)

    return 0;
@@ -735,7 +765,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) { 
          TmpOffset += SL->getElementOffset(Idx);

        } else {

          uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());

          for (;;) {

          while (true) {

            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {

              // Constant-offset addressing.

              TmpOffset += CI->getSExtValue() * S;
@@ -1212,7 +1242,6 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { 
  // behavior.

  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {

    if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {



      // Get the compare predicate.

      // Try to take advantage of fallthrough opportunities.

      CmpInst::Predicate Predicate = CI->getPredicate();
@@ -2429,9 +2458,9 @@ bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, 
    bool RV;

    unsigned ResultReg;

    RV = ARMEmitLoad(VT, ResultReg, Src);

    assert (RV == true && "Should be able to handle this load.");

    assert(RV && "Should be able to handle this load.");

    RV = ARMEmitStore(VT, ResultReg, Dest);

    assert (RV == true && "Should be able to handle this store.");

    assert(RV && "Should be able to handle this store.");

    (void)RV;



    unsigned Size = VT.getSizeInBits()/8;
@@ -2777,7 +2806,6 @@ bool ARMFastISel::SelectShift(const Instruction *I, 


// TODO: SoftFP support.

bool ARMFastISel::fastSelectInstruction(const Instruction *I) {



  switch (I->getOpcode()) {

    case Instruction::Load:

      return SelectLoad(I);
@@ -2847,6 +2875,7 @@ bool ARMFastISel::fastSelectInstruction(const Instruction *I) { 
}



namespace {



// This table describes sign- and zero-extend instructions which can be

// folded into a preceding load. All of these extends have an immediate

// (sometimes a mask and sometimes a shift) that's applied after
@@ -2863,7 +2892,8 @@ const struct FoldableLoadExtendsStruct { 
  { { ARM::SXTB,  ARM::t2SXTB  },   0, 0, MVT::i8  },

  { { ARM::UXTB,  ARM::t2UXTB  },   0, 1, MVT::i8  }

};

}



} // end anonymous namespace



/// \brief The specified machine instr operand is a vreg, and that

/// vreg is being provided by the specified load instruction.  If possible,
@@ -3008,7 +3038,6 @@ bool ARMFastISel::fastLowerArguments() { 
    }

  }





  static const MCPhysReg GPRArgRegs[] = {

    ARM::R0, ARM::R1, ARM::R2, ARM::R3

  };
@@ -3033,6 +3062,7 @@ bool ARMFastISel::fastLowerArguments() { 
}



namespace llvm {



  FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,

                                const TargetLibraryInfo *libInfo) {

    if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
@@ -3040,4 +3070,5 @@ namespace llvm { 


    return nullptr;

  }

}
 


} // end namespace llvm

llvm/lib/Target/ARM/ARMTargetMachine.cpp

+52 −25
Original line number Diff line number Diff line
@@ -10,30 +10,49 @@ 
//

//===----------------------------------------------------------------------===//



#include "ARMTargetMachine.h"

#include "ARM.h"

#include "ARMCallLowering.h"

#include "ARMFrameLowering.h"

#include "ARMInstructionSelector.h"

#include "ARMLegalizerInfo.h"

#include "ARMRegisterBankInfo.h"

#include "ARMSubtarget.h"

#include "ARMTargetMachine.h"

#include "ARMTargetObjectFile.h"

#include "ARMTargetTransformInfo.h"

#include "MCTargetDesc/ARMMCTargetDesc.h"

#include "llvm/ADT/Optional.h"

#include "llvm/ADT/STLExtras.h"

#include "llvm/ADT/StringRef.h"

#include "llvm/ADT/Triple.h"

#include "llvm/Analysis/TargetTransformInfo.h"

#include "llvm/CodeGen/GlobalISel/CallLowering.h"

#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"

#include "llvm/CodeGen/GlobalISel/IRTranslator.h"

#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"

#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"

#include "llvm/CodeGen/GlobalISel/Legalizer.h"

#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"

#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"

#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"

#include "llvm/CodeGen/MachineFunction.h"

#include "llvm/CodeGen/Passes.h"

#include "llvm/CodeGen/TargetPassConfig.h"

#include "llvm/IR/Attributes.h"

#include "llvm/IR/DataLayout.h"

#include "llvm/IR/Function.h"

#include "llvm/IR/LegacyPassManager.h"

#include "llvm/MC/MCAsmInfo.h"

#include "llvm/Pass.h"

#include "llvm/Support/CodeGen.h"

#include "llvm/Support/CommandLine.h"

#include "llvm/Support/FormattedStream.h"

#include "llvm/Support/ErrorHandling.h"

#include "llvm/Support/TargetParser.h"

#include "llvm/Support/TargetRegistry.h"

#include "llvm/Target/TargetLoweringObjectFile.h"

#include "llvm/Target/TargetOptions.h"

#include "llvm/Transforms/Scalar.h"

#include <cassert>

#include <memory>

#include <string>



using namespace llvm;



static cl::opt<bool>
@@ -72,10 +91,10 @@ extern "C" void LLVMInitializeARMTarget() { 


static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {

  if (TT.isOSBinFormatMachO())

    return make_unique<TargetLoweringObjectFileMachO>();

    return llvm::make_unique<TargetLoweringObjectFileMachO>();

  if (TT.isOSWindows())

    return make_unique<TargetLoweringObjectFileCOFF>();

  return make_unique<ARMElfTargetObjectFile>();

    return llvm::make_unique<TargetLoweringObjectFileCOFF>();

  return llvm::make_unique<ARMElfTargetObjectFile>();

}



static ARMBaseTargetMachine::ARMABI
@@ -94,13 +113,13 @@ computeTargetABI(const Triple &TT, StringRef CPU, 
  ARMBaseTargetMachine::ARMABI TargetABI =

      ARMBaseTargetMachine::ARM_ABI_UNKNOWN;



  unsigned ArchKind = llvm::ARM::parseCPUArch(CPU);

  StringRef ArchName = llvm::ARM::getArchName(ArchKind);

  unsigned ArchKind = ARM::parseCPUArch(CPU);

  StringRef ArchName = ARM::getArchName(ArchKind);

  // FIXME: This is duplicated code from the front end and should be unified.

  if (TT.isOSBinFormatMachO()) {

    if (TT.getEnvironment() == llvm::Triple::EABI ||

        (TT.getOS() == llvm::Triple::UnknownOS && TT.isOSBinFormatMachO()) ||

        llvm::ARM::parseArchProfile(ArchName) == llvm::ARM::PK_M) {

    if (TT.getEnvironment() == Triple::EABI ||

        (TT.getOS() == Triple::UnknownOS && TT.isOSBinFormatMachO()) ||

        ARM::parseArchProfile(ArchName) == ARM::PK_M) {

      TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;

    } else if (TT.isWatchABI()) {

      TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS16;
@@ -113,16 +132,16 @@ computeTargetABI(const Triple &TT, StringRef CPU, 
  } else {

    // Select the default based on the platform.

    switch (TT.getEnvironment()) {

    case llvm::Triple::Android:

    case llvm::Triple::GNUEABI:

    case llvm::Triple::GNUEABIHF:

    case llvm::Triple::MuslEABI:

    case llvm::Triple::MuslEABIHF:

    case llvm::Triple::EABIHF:

    case llvm::Triple::EABI:

    case Triple::Android:

    case Triple::GNUEABI:

    case Triple::GNUEABIHF:

    case Triple::MuslEABI:

    case Triple::MuslEABIHF:

    case Triple::EABIHF:

    case Triple::EABI:

      TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;

      break;

    case llvm::Triple::GNU:

    case Triple::GNU:

      TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;

      break;

    default:
@@ -141,7 +160,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, 
                                     const TargetOptions &Options,

                                     bool isLittle) {

  auto ABI = computeTargetABI(TT, CPU, Options);

  std::string Ret = "";

  std::string Ret;



  if (isLittle)

    // Little endian.
@@ -238,29 +257,35 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, 
  }

}



ARMBaseTargetMachine::~ARMBaseTargetMachine() {}

ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;



#ifdef LLVM_BUILD_GLOBAL_ISEL

namespace {



struct ARMGISelActualAccessor : public GISelAccessor {

  std::unique_ptr<CallLowering> CallLoweringInfo;

  std::unique_ptr<InstructionSelector> InstSelector;

  std::unique_ptr<LegalizerInfo> Legalizer;

  std::unique_ptr<RegisterBankInfo> RegBankInfo;



  const CallLowering *getCallLowering() const override {

    return CallLoweringInfo.get();

  }



  const InstructionSelector *getInstructionSelector() const override {

    return InstSelector.get();

  }



  const LegalizerInfo *getLegalizerInfo() const override {

    return Legalizer.get();

  }



  const RegisterBankInfo *getRegBankInfo() const override {

    return RegBankInfo.get();

  }

};

} // End anonymous namespace.



} // end anonymous namespace

#endif



const ARMSubtarget *
@@ -390,6 +415,7 @@ ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, const Triple &TT, 
    : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}



namespace {



/// ARM Code Generator Pass Configuration Options.

class ARMPassConfig : public TargetPassConfig {

public:
@@ -413,7 +439,8 @@ public: 
  void addPreSched2() override;

  void addPreEmitPass() override;

};

} // namespace



} // end anonymous namespace



TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {

  return new ARMPassConfig(this, PM);