Commit 3382c243 authored by Jessica Clarke's avatar Jessica Clarke
Browse files

[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos 

Summary:
Without these, the generic branch relaxation pass will underestimate the
range required for branches spanning these and we can end up with
"fixup value out of range" errors rather than relaxing the branches.
Some of the instructions in the expansion may end up being compressed
but exactly determining that is awkward, and these conservative values
should be safe, if slightly suboptimal in rare cases.

Reviewers: asb, lenary, luismarques, lewis-revill

Reviewed By: asb, luismarques

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77443
parent 7a587ca9

llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp

+3 −0
Original line number Diff line number Diff line
@@ -86,6 +86,9 @@ bool RISCVExpandAtomicPseudo::expandMBB(MachineBasicBlock &MBB) { 
bool RISCVExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB,

                                       MachineBasicBlock::iterator MBBI,

                                       MachineBasicBlock::iterator &NextMBBI) {

  // RISCVInstrInfo::getInstSizeInBytes hard-codes the number of expanded

  // instructions for each pseudo, and must be updated when adding new pseudos

  // or changing existing ones.

  switch (MBBI->getOpcode()) {

  case RISCV::PseudoAtomicLoadNand32:

    return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 32,

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

+3 −0
Original line number Diff line number Diff line
@@ -87,6 +87,9 @@ bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) { 
bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,

                                 MachineBasicBlock::iterator MBBI,

                                 MachineBasicBlock::iterator &NextMBBI) {

  // RISCVInstrInfo::getInstSizeInBytes hard-codes the number of expanded

  // instructions for each pseudo, and must be updated when adding new pseudos

  // or changing existing ones.

  switch (MBBI->getOpcode()) {

  case RISCV::PseudoLLA:

    return expandLoadLocalAddress(MBB, MBBI, NextMBBI);

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

+23 −0
Original line number Diff line number Diff line
@@ -471,6 +471,9 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { 
  case TargetOpcode::KILL:

  case TargetOpcode::DBG_VALUE:

    return 0;

  // These values are determined based on RISCVExpandAtomicPseudoInsts,

  // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the

  // pseudos are expanded.

  case RISCV::PseudoCALLReg:

  case RISCV::PseudoCALL:

  case RISCV::PseudoJump:
@@ -480,6 +483,26 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { 
  case RISCV::PseudoLA_TLS_IE:

  case RISCV::PseudoLA_TLS_GD:

    return 8;

  case RISCV::PseudoAtomicLoadNand32:

  case RISCV::PseudoAtomicLoadNand64:

    return 20;

  case RISCV::PseudoMaskedAtomicSwap32:

  case RISCV::PseudoMaskedAtomicLoadAdd32:

  case RISCV::PseudoMaskedAtomicLoadSub32:

    return 28;

  case RISCV::PseudoMaskedAtomicLoadNand32:

    return 32;

  case RISCV::PseudoMaskedAtomicLoadMax32:

  case RISCV::PseudoMaskedAtomicLoadMin32:

    return 44;

  case RISCV::PseudoMaskedAtomicLoadUMax32:

  case RISCV::PseudoMaskedAtomicLoadUMin32:

    return 36;

  case RISCV::PseudoCmpXchg32:

  case RISCV::PseudoCmpXchg64:

    return 16;

  case RISCV::PseudoMaskedCmpXchg32:

    return 32;

  case TargetOpcode::INLINEASM:

  case TargetOpcode::INLINEASM_BR: {

    const MachineFunction &MF = *MI.getParent()->getParent();