Loading clang/lib/CIR/CodeGen/CIRGenExpr.cpp +13 −3 Original line number Diff line number Diff line Loading @@ -1551,11 +1551,21 @@ LValue CIRGenFunction::emitExtVectorElementExpr(const ExtVectorElementExpr *e) { base.getBaseInfo()); } cgm.errorNYI(e->getSourceRange(), "emitExtVectorElementExpr: isSimple is false"); if (base.isMatrixRow()) { cgm.errorNYI(e->getSourceRange(), "emitExtVectorElementExpr: isMatrixRow"); return {}; } assert(base.isExtVectorElt() && "Can only subscript lvalue vec elts here!"); mlir::ArrayAttr baseElts = base.getExtVectorElts(); SmallVector<int64_t> elts; for (unsigned idx : indices) elts.push_back(getAccessedFieldNo(idx, baseElts)); mlir::ArrayAttr cv = builder.getI64ArrayAttr(elts); return LValue::makeExtVectorElt(base.getAddress(), cv, type, base.getBaseInfo()); } LValue CIRGenFunction::emitStringLiteralLValue(const StringLiteral *e, llvm::StringRef name) { cir::GlobalOp globalOp = cgm.getGlobalForStringLiteral(e, name); Loading clang/lib/CIR/CodeGen/CIRGenValue.h +3 −1 Original line number Diff line number Diff line Loading @@ -158,7 +158,8 @@ class LValue { BitField, // This is a bitfield l-value, use getBitfield*. ExtVectorElt, // This is an extended vector subset, use getExtVectorComp GlobalReg, // This is a register l-value, use getGlobalReg() MatrixElt // This is a matrix element, use getVector* MatrixElt, // This is a matrix element, use getVector* MatrixRow // This is a matrix vector subset, use getVector* } lvType; clang::QualType type; clang::Qualifiers quals; Loading Loading @@ -194,6 +195,7 @@ public: bool isBitField() const { return lvType == BitField; } bool isExtVectorElt() const { return lvType == ExtVectorElt; } bool isGlobalReg() const { return lvType == GlobalReg; } bool isMatrixRow() const { return lvType == MatrixRow; } bool isVolatile() const { return quals.hasVolatile(); } bool isVolatileQualified() const { return quals.hasVolatile(); } Loading clang/test/CIR/CodeGen/vector-ext-element.cpp +24 −0 Original line number Diff line number Diff line Loading @@ -402,3 +402,27 @@ void store_src_dest_not_same_size() { // OGCG: %[[SHUFFLE_A:.*]] = shufflevector <2 x i32> %[[TMP_B]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> // OGCG: %[[RESULT:.*]] = shufflevector <4 x i32> %[[TMP_A]], <4 x i32> %[[SHUFFLE_A]], <4 x i32> <i32 4, i32 5, i32 2, i32 3> // OGCG: store <4 x i32> %[[RESULT]], ptr %[[A_ADDR]], align 16 void non_simple_base() { vi4 a; int b = a.xy.x; } // CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a"] // CIR: %[[B_ADDR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["b", init] // CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> // CIR: %[[CONST_0:.*]] = cir.const #cir.int<0> : !s64i // CIR: %[[RESULT:.*]] = cir.vec.extract %[[TMP_A]][%[[CONST_0]] : !s64i] : !cir.vector<4 x !s32i> // CIR: cir.store {{.*}} %[[RESULT]], %[[B_ADDR]] : !s32i, !cir.ptr<!s32i> // LLVM: %[[A_ADDR:.*]] = alloca <4 x i32> // LLVM: %[[B_ADDR]] = alloca i32 // LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16 // LLVM: %[[RESULT:.*]] = extractelement <4 x i32> %[[TMP_A]], i64 0 // LLVM: store i32 %[[RESULT]], ptr %[[B_ADDR]], align 4 // OGCG: %[[A_ADDR:.*]] = alloca <4 x i32>, align 16 // OGCG: %[[B_ADDR]] = alloca i32, align 4 // OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16 // OGCG: %[[RESULT:.*]] = extractelement <4 x i32> %[[TMP_A]], i64 0 // OGCG: store i32 %[[RESULT]], ptr %[[B_ADDR]], align 4 Loading
clang/lib/CIR/CodeGen/CIRGenExpr.cpp +13 −3 Original line number Diff line number Diff line Loading @@ -1551,11 +1551,21 @@ LValue CIRGenFunction::emitExtVectorElementExpr(const ExtVectorElementExpr *e) { base.getBaseInfo()); } cgm.errorNYI(e->getSourceRange(), "emitExtVectorElementExpr: isSimple is false"); if (base.isMatrixRow()) { cgm.errorNYI(e->getSourceRange(), "emitExtVectorElementExpr: isMatrixRow"); return {}; } assert(base.isExtVectorElt() && "Can only subscript lvalue vec elts here!"); mlir::ArrayAttr baseElts = base.getExtVectorElts(); SmallVector<int64_t> elts; for (unsigned idx : indices) elts.push_back(getAccessedFieldNo(idx, baseElts)); mlir::ArrayAttr cv = builder.getI64ArrayAttr(elts); return LValue::makeExtVectorElt(base.getAddress(), cv, type, base.getBaseInfo()); } LValue CIRGenFunction::emitStringLiteralLValue(const StringLiteral *e, llvm::StringRef name) { cir::GlobalOp globalOp = cgm.getGlobalForStringLiteral(e, name); Loading
clang/lib/CIR/CodeGen/CIRGenValue.h +3 −1 Original line number Diff line number Diff line Loading @@ -158,7 +158,8 @@ class LValue { BitField, // This is a bitfield l-value, use getBitfield*. ExtVectorElt, // This is an extended vector subset, use getExtVectorComp GlobalReg, // This is a register l-value, use getGlobalReg() MatrixElt // This is a matrix element, use getVector* MatrixElt, // This is a matrix element, use getVector* MatrixRow // This is a matrix vector subset, use getVector* } lvType; clang::QualType type; clang::Qualifiers quals; Loading Loading @@ -194,6 +195,7 @@ public: bool isBitField() const { return lvType == BitField; } bool isExtVectorElt() const { return lvType == ExtVectorElt; } bool isGlobalReg() const { return lvType == GlobalReg; } bool isMatrixRow() const { return lvType == MatrixRow; } bool isVolatile() const { return quals.hasVolatile(); } bool isVolatileQualified() const { return quals.hasVolatile(); } Loading
clang/test/CIR/CodeGen/vector-ext-element.cpp +24 −0 Original line number Diff line number Diff line Loading @@ -402,3 +402,27 @@ void store_src_dest_not_same_size() { // OGCG: %[[SHUFFLE_A:.*]] = shufflevector <2 x i32> %[[TMP_B]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> // OGCG: %[[RESULT:.*]] = shufflevector <4 x i32> %[[TMP_A]], <4 x i32> %[[SHUFFLE_A]], <4 x i32> <i32 4, i32 5, i32 2, i32 3> // OGCG: store <4 x i32> %[[RESULT]], ptr %[[A_ADDR]], align 16 void non_simple_base() { vi4 a; int b = a.xy.x; } // CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a"] // CIR: %[[B_ADDR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["b", init] // CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> // CIR: %[[CONST_0:.*]] = cir.const #cir.int<0> : !s64i // CIR: %[[RESULT:.*]] = cir.vec.extract %[[TMP_A]][%[[CONST_0]] : !s64i] : !cir.vector<4 x !s32i> // CIR: cir.store {{.*}} %[[RESULT]], %[[B_ADDR]] : !s32i, !cir.ptr<!s32i> // LLVM: %[[A_ADDR:.*]] = alloca <4 x i32> // LLVM: %[[B_ADDR]] = alloca i32 // LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16 // LLVM: %[[RESULT:.*]] = extractelement <4 x i32> %[[TMP_A]], i64 0 // LLVM: store i32 %[[RESULT]], ptr %[[B_ADDR]], align 4 // OGCG: %[[A_ADDR:.*]] = alloca <4 x i32>, align 16 // OGCG: %[[B_ADDR]] = alloca i32, align 4 // OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16 // OGCG: %[[RESULT:.*]] = extractelement <4 x i32> %[[TMP_A]], i64 0 // OGCG: store i32 %[[RESULT]], ptr %[[B_ADDR]], align 4