Commit 3296a833 authored Nov 16, 2015 by Tom Stellard

Merging r243661:

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r243661 | Matthew.Arsenault | 2015-07-30 13:03:11 -0400 (Thu, 30 Jul 2015) | 6 lines

AMDGPU: Set SubRegIndex size and offset

I'm not sure what reasons the comment here could have
had for not setting these. Without these set, there is
an assertion hit during DWARF emission.

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llvm-svn: 253230

parent a115a22d

llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td

+1 −2

Original line number	Diff line number	Diff line
		@@ -14,8 +14,7 @@
		let Namespace = "AMDGPU" in {

		foreach Index = 0-15 in {
		// Indices are used in a variety of ways here, so don't set a size/offset.
		def sub#Index : SubRegIndex<-1, -1>;
		def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
		}

		def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;