Commit 30082a16 authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r275981 and r276740: 

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r275981 | rksimon | 2016-07-19 08:07:43 -0700 (Tue, 19 Jul 2016) | 13 lines

[X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using generic IR

D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead.

It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match).

This patch changes both scalar and packed versions back to using x86-specific builtins.

It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding.

A companion clang patch is at D22105

Differential Revision: https://reviews.llvm.org/D22106
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r276740 | rksimon | 2016-07-26 03:41:28 -0700 (Tue, 26 Jul 2016) | 5 lines

[X86][SSE] Fixed issue with memory folding of (v)cvtsd2ss intrinsics

Fixed typo in the intrinsic definitions of (v)cvtsd2ss with memory folding.

This was only unearthed when rL276102 started using the intrinsic again.....
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llvm-svn: 276990
parent b3c29bd1

llvm/include/llvm/IR/IntrinsicsX86.td

+6 −0
Original line number Diff line number Diff line
@@ -479,6 +479,8 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". 
              Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty], [IntrNoMem]>;

  def int_x86_sse2_cvtps2dq : GCCBuiltin<"__builtin_ia32_cvtps2dq">,

              Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;

  def int_x86_sse2_cvttps2dq : GCCBuiltin<"__builtin_ia32_cvttps2dq">,

              Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;

  def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">,

              Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;

  def int_x86_sse2_cvtsd2si64 : GCCBuiltin<"__builtin_ia32_cvtsd2si64">,
@@ -1512,8 +1514,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". 
        Intrinsic<[llvm_v4f32_ty], [llvm_v4f64_ty], [IntrNoMem]>;

  def int_x86_avx_cvt_ps2dq_256 : GCCBuiltin<"__builtin_ia32_cvtps2dq256">,

        Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;

  def int_x86_avx_cvtt_pd2dq_256 : GCCBuiltin<"__builtin_ia32_cvttpd2dq256">,

        Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;

  def int_x86_avx_cvt_pd2dq_256 : GCCBuiltin<"__builtin_ia32_cvtpd2dq256">,

        Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;

  def int_x86_avx_cvtt_ps2dq_256 : GCCBuiltin<"__builtin_ia32_cvttps2dq256">,

        Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;

}



// Vector bit test

llvm/lib/Analysis/ConstantFolding.cpp

+10 −9
Original line number Diff line number Diff line
@@ -1424,7 +1424,7 @@ Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double), double V, 
/// integer type Ty is used to select how many bits are available for the

/// result. Returns null if the conversion cannot be performed, otherwise

/// returns the Constant value resulting from the conversion.

Constant *ConstantFoldConvertToInt(const APFloat &Val, bool roundTowardZero,

Constant *ConstantFoldSSEConvertToInt(const APFloat &Val, bool roundTowardZero,

                                      Type *Ty) {

  // All of these conversion intrinsics form an integer of at most 64bits.

  unsigned ResultWidth = Ty->getIntegerBitWidth();
@@ -1438,7 +1438,8 @@ Constant *ConstantFoldConvertToInt(const APFloat &Val, bool roundTowardZero, 
  APFloat::opStatus status = Val.convertToInteger(&UIntVal, ResultWidth,

                                                  /*isSigned=*/true, mode,

                                                  &isExact);

  if (status != APFloat::opOK && status != APFloat::opInexact)

  if (status != APFloat::opOK &&

      (!roundTowardZero || status != APFloat::opInexact))

    return nullptr;

  return ConstantInt::get(Ty, UIntVal, /*isSigned=*/true);

}
@@ -1677,7 +1678,7 @@ Constant *ConstantFoldScalarCall(StringRef Name, unsigned IntrinsicID, Type *Ty, 
      case Intrinsic::x86_sse2_cvtsd2si64:

        if (ConstantFP *FPOp =

                dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))

          return ConstantFoldConvertToInt(FPOp->getValueAPF(),

          return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),

                                             /*roundTowardZero=*/false, Ty);

      case Intrinsic::x86_sse_cvttss2si:

      case Intrinsic::x86_sse_cvttss2si64:
@@ -1685,7 +1686,7 @@ Constant *ConstantFoldScalarCall(StringRef Name, unsigned IntrinsicID, Type *Ty, 
      case Intrinsic::x86_sse2_cvttsd2si64:

        if (ConstantFP *FPOp =

                dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))

          return ConstantFoldConvertToInt(FPOp->getValueAPF(),

          return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),

                                             /*roundTowardZero=*/true, Ty);

      }

    }

llvm/lib/IR/AutoUpgrade.cpp

+0 −8
Original line number Diff line number Diff line
@@ -251,8 +251,6 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 
         Name == "sse2.cvtps2pd" ||

         Name == "avx.cvtdq2.pd.256" ||

         Name == "avx.cvt.ps2.pd.256" ||

         Name == "sse2.cvttps2dq" ||

         Name.startswith("avx.cvtt.") ||

         Name.startswith("avx.vinsertf128.") ||

         Name == "avx2.vinserti128" ||

         Name.startswith("avx.vextractf128.") ||
@@ -712,12 +710,6 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 
        Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd");

      else

        Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd");

    } else if (IsX86 && (Name == "sse2.cvttps2dq" ||

                         Name.startswith("avx.cvtt."))) {

      // Truncation (round to zero) float/double to i32 vector conversion.

      Value *Src = CI->getArgOperand(0);

      VectorType *DstTy = cast<VectorType>(CI->getType());

      Rep = Builder.CreateFPToSI(Src, DstTy, "cvtt");

    } else if (IsX86 && Name.startswith("sse4a.movnt.")) {

      Module *M = F->getParent();

      SmallVector<Metadata *, 1> Elts;

llvm/lib/Target/X86/X86InstrSSE.td

+25 −10
Original line number Diff line number Diff line
@@ -1820,7 +1820,7 @@ def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg, 
                         (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],

                       IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,

                       Sched<[WriteCvtF2F]>;

def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,

def Int_VCVTSD2SSrm: I<0x5A, MRMSrcMem,

                       (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),

                       "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",

                       [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
@@ -1836,7 +1836,7 @@ def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg, 
                         (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],

                       IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,

                       Sched<[WriteCvtF2F]>;

def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,

def Int_CVTSD2SSrm: I<0x5A, MRMSrcMem,

                       (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),

                       "cvtsd2ss\t{$src2, $dst|$dst, $src2}",

                       [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
@@ -2009,24 +2009,35 @@ def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 
// SSE2 packed instructions with XS prefix

def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),

                         "cvttps2dq\t{$src, $dst|$dst, $src}",

                         [], IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;

                         [(set VR128:$dst,

                           (int_x86_sse2_cvttps2dq VR128:$src))],

                         IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;

def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),

                         "cvttps2dq\t{$src, $dst|$dst, $src}",

                         [], IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;

                         [(set VR128:$dst, (int_x86_sse2_cvttps2dq

                                            (loadv4f32 addr:$src)))],

                         IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;

def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),

                          "cvttps2dq\t{$src, $dst|$dst, $src}",

                          [], IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;

                          [(set VR256:$dst,

                            (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],

                          IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;

def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),

                          "cvttps2dq\t{$src, $dst|$dst, $src}",

                          [], IIC_SSE_CVT_PS_RM>, VEX, VEX_L,

                          [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256

                                             (loadv8f32 addr:$src)))],

                          IIC_SSE_CVT_PS_RM>, VEX, VEX_L,

                          Sched<[WriteCvtF2ILd]>;



def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),

                       "cvttps2dq\t{$src, $dst|$dst, $src}",

                       [], IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;

                       [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],

                       IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;

def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),

                       "cvttps2dq\t{$src, $dst|$dst, $src}",

                       [], IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;

                       [(set VR128:$dst,

                         (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],

                       IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;



let Predicates = [HasAVX] in {

  def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
@@ -2096,10 +2107,14 @@ def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), 
// YMM only

def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),

                         "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",

                         [], IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;

                         [(set VR128:$dst,

                           (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],

                         IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;

def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),

                         "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",

                         [], IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;

                         [(set VR128:$dst,

                          (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],

                         IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;

def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",

                (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;

llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll

+4 −2
Original line number Diff line number Diff line
@@ -681,10 +681,11 @@ define <2 x i64> @test_mm256_cvttpd_epi32(<4 x double> %a0) nounwind { 
; X64-NEXT:    vcvttpd2dqy %ymm0, %xmm0

; X64-NEXT:    vzeroupper

; X64-NEXT:    retq

  %cvt = fptosi <4 x double> %a0 to <4 x i32>

  %cvt = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0)

  %res = bitcast <4 x i32> %cvt to <2 x i64>

  ret <2 x i64> %res

}

declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone



define <4 x i64> @test_mm256_cvttps_epi32(<8 x float> %a0) nounwind {

; X32-LABEL: test_mm256_cvttps_epi32:
@@ -696,10 +697,11 @@ define <4 x i64> @test_mm256_cvttps_epi32(<8 x float> %a0) nounwind { 
; X64:       # BB#0:

; X64-NEXT:    vcvttps2dq %ymm0, %ymm0

; X64-NEXT:    retq

  %cvt = fptosi <8 x float> %a0 to <8 x i32>

  %cvt = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0)

  %res = bitcast <8 x i32> %cvt to <4 x i64>

  ret <4 x i64> %res

}

declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone



define <4 x double> @test_mm256_div_pd(<4 x double> %a0, <4 x double> %a1) nounwind {

; X32-LABEL: test_mm256_div_pd: