Commit 2b66d32f authored by Petar Avramovic's avatar Petar Avramovic
Browse files

[MIPS GlobalISel] Select count leading zeros 

llvm.ctlz.<type> intrinsic has additional i1 argument is_zero_undef,
it tells whether zero as the first argument produces a defined result.
MIPS clz instruction returns 32 for zero input.
G_CTLZ is generated from llvm.ctlz.<type> (<type> <src>, i1 false)
intrinsics, clang generates these intrinsics from __builtin_clz and
__builtin_clzll.
G_CTLZ_ZERO_UNDEF can also be generated from llvm.ctlz with true as
second argument. It is also traditionally part of and many algorithms
that are now predicated on avoiding zero-value inputs.

Add narrow scalar for G_CTLZ (algorithm uses G_CTLZ_ZERO_UNDEF).
Lower G_CTLZ_ZERO_UNDEF and select G_CTLZ for MIPS32.

Differential Revision: https://reviews.llvm.org/D73214
parent 941f20c3

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

+1 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ public: 
  LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

  LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

  LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

  LegalizeResult narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);



  LegalizeResult lowerBitcast(MachineInstr &MI);

  LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

+38 −2
Original line number Diff line number Diff line
@@ -977,8 +977,13 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 
  case TargetOpcode::G_CTTZ:

  case TargetOpcode::G_CTTZ_ZERO_UNDEF:

  case TargetOpcode::G_CTPOP:

    if (TypeIdx != 0)

      return UnableToLegalize; // TODO

    if (TypeIdx == 1)

      switch (MI.getOpcode()) {

      case TargetOpcode::G_CTLZ:

        return narrowScalarCTLZ(MI, TypeIdx, NarrowTy);

      default:

        return UnableToLegalize;

      }



    Observer.changingInstr(MI);

    narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
@@ -3849,6 +3854,37 @@ LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 
  return Legalized;

}



LegalizerHelper::LegalizeResult

LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,

                                  LLT NarrowTy) {

  if (TypeIdx != 1)

    return UnableToLegalize;



  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

  unsigned NarrowSize = NarrowTy.getSizeInBits();



  if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {

    MachineIRBuilder &B = MIRBuilder;

    auto UnmergeSrc = B.buildUnmerge(NarrowTy, MI.getOperand(1));

    // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi)

    auto C_0 = B.buildConstant(NarrowTy, 0);

    auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),

                                UnmergeSrc.getReg(1), C_0);

    auto LoCTLZ = B.buildCTLZ(NarrowTy, UnmergeSrc.getReg(0));

    auto C_NarrowSize = B.buildConstant(NarrowTy, NarrowSize);

    auto HiIsZeroCTLZ = B.buildAdd(NarrowTy, LoCTLZ, C_NarrowSize);

    auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(NarrowTy, UnmergeSrc.getReg(1));

    auto LoOut = B.buildSelect(NarrowTy, HiIsZero, HiIsZeroCTLZ, HiCTLZ);



    B.buildMerge(MI.getOperand(0), {LoOut.getReg(0), C_0.getReg(0)});



    MI.eraseFromParent();

    return Legalized;

  }



  return UnableToLegalize;

}



LegalizerHelper::LegalizeResult

LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {

  unsigned Opc = MI.getOpcode();

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

+6 −0
Original line number Diff line number Diff line
@@ -202,6 +202,12 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { 
      .lowerFor({s32})

      .maxScalar(0, s32);



  getActionDefinitionsBuilder(G_CTLZ)

      .legalFor({{s32, s32}})

      .maxScalar(1, s32);

  getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)

      .lowerFor({{s32, s32}});



  // FP instructions

  getActionDefinitionsBuilder(G_FCONSTANT)

      .legalFor({s32, s64});

llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

+1 −0
Original line number Diff line number Diff line
@@ -453,6 +453,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
  case G_BRINDIRECT:

  case G_VASTART:

  case G_BSWAP:

  case G_CTLZ:

    OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];

    break;

  case G_ADD:

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir

0 → 100644
+24 −0
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32

---

name:            ctlz_i32

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  bb.1.entry:

    liveins: $a0



    ; MIPS32-LABEL: name: ctlz_i32

    ; MIPS32: liveins: $a0

    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0

    ; MIPS32: [[CLZ:%[0-9]+]]:gpr32 = CLZ [[COPY]]

    ; MIPS32: $v0 = COPY [[CLZ]]

    ; MIPS32: RetRA implicit $v0

    %0:gprb(s32) = COPY $a0

    %1:gprb(s32) = G_CTLZ %0(s32)

    $v0 = COPY %1(s32)

    RetRA implicit $v0



...