Commit 2a160ba5 authored by Matt Arsenault's avatar Matt Arsenault
Browse files

GlobalISel: Reimplement widenScalar for G_UNMERGE_VALUES results 

Only use shifts if the requested type exactly matches the source type,
and create sub-unmerges otherwise.
parent 8a6b948e

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

+54 −14
Original line number Diff line number Diff line
@@ -1396,7 +1396,7 @@ LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 
  if (TypeIdx != 0)

    return UnableToLegalize;



  unsigned NumDst = MI.getNumOperands() - 1;

  int NumDst = MI.getNumOperands() - 1;

  Register SrcReg = MI.getOperand(NumDst).getReg();

  LLT SrcTy = MRI.getType(SrcReg);

  if (!SrcTy.isScalar())
@@ -1407,26 +1407,66 @@ LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 
  if (!DstTy.isScalar())

    return UnableToLegalize;



  unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();

  LLT NewSrcTy = LLT::scalar(NewSrcSize);

  unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();

  if (WideTy == SrcTy) {

    // Theres no unmerge type to target. Directly extract the bits from the

    // source type

    unsigned DstSize = DstTy.getSizeInBits();



  auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);

    MIRBuilder.buildTrunc(Dst0Reg, SrcReg);

    for (int I = 1; I != NumDst; ++I) {

      auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I);

      auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt);

      MIRBuilder.buildTrunc(MI.getOperand(I), Shr);

    }



  for (unsigned I = 1; I != NumDst; ++I) {

    auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);

    auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);

    WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);

    MI.eraseFromParent();

    return Legalized;

  }



  Observer.changingInstr(MI);

  // TODO

  if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())

    return UnableToLegalize;



  MI.getOperand(NumDst).setReg(WideSrc.getReg(0));

  for (unsigned I = 0; I != NumDst; ++I)

    widenScalarDst(MI, WideTy, I);

  // Extend the source to a wider type.

  LLT LCMTy = getLCMType(SrcTy, WideTy);



  Observer.changedInstr(MI);

  Register WideSrc = SrcReg;

  if (LCMTy != SrcTy)

    WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0);

  auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc);



  // Create a sequence of unmerges to the original results. since we may have

  // widened the source, we will need to pad the results with dead defs to cover

  // the source register.

  // e.g. widen s16 to s32:

  // %1:_(s16), %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0:_(s48)

  //

  // =>

  //  %4:_(s64) = G_ANYEXT %0:_(s48)

  //  %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %4 ; Requested unmerge

  //  %1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %5 ; unpack to original regs

  //  %3:_(s16), dead %7 = G_UNMERGE_VALUES %6 ; original reg + extra dead def



  const int NumUnmerge = Unmerge->getNumOperands() - 1;

  const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits();



  for (int I = 0; I != NumUnmerge; ++I) {

    auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);



    for (int J = 0; J != PartsPerUnmerge; ++J) {

      int Idx = I * PartsPerUnmerge + J;

      if (Idx < NumDst)

        MIB.addDef(MI.getOperand(Idx).getReg());

      else {

        // Create dead def for excess components.

        MIB.addDef(MRI.createGenericVirtualRegister(DstTy));

      }

    }



    MIB.addUse(Unmerge.getReg(I));

  }



  MI.eraseFromParent();

  return Legalized;

}

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

+11 −7
Original line number Diff line number Diff line
@@ -1029,16 +1029,21 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, 
    };



    auto &Builder = getActionDefinitionsBuilder(Op)

      // Try to widen to s16 first for small types.

      // TODO: Only do this on targets with legal s16 shifts

      .minScalarOrEltIf(narrowerThan(LitTyIdx, 16), LitTyIdx, S16)



      .widenScalarToNextPow2(LitTyIdx, /*Min*/ 16)

      // Clamp the little scalar to s8-s256 and make it a power of 2. It's not

      // worth considering the multiples of 64 since 2*192 and 2*384 are not

      // valid.

      .clampScalar(LitTyIdx, S16, S256)

      .widenScalarToNextPow2(LitTyIdx, /*Min*/ 32)

      .lowerFor({{S16, V2S16}})

      .moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))

      .fewerElementsIf(all(typeIs(0, S16), vectorWiderThan(1, 32),

                           elementTypeIs(1, S16)),

                       changeTo(1, V2S16))

      // Clamp the little scalar to s8-s256 and make it a power of 2. It's not

      // worth considering the multiples of 64 since 2*192 and 2*384 are not

      // valid.

      .clampScalar(LitTyIdx, S32, S256)

      .widenScalarToNextPow2(LitTyIdx, /*Min*/ 32)

      // Break up vectors with weird elements into scalars

      .fewerElementsIf(

        [=](const LegalityQuery &Query) { return notValidElt(Query, 0); },
@@ -1046,8 +1051,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, 
      .fewerElementsIf(

        [=](const LegalityQuery &Query) { return notValidElt(Query, 1); },

        scalarize(1))

      .clampScalar(BigTyIdx, S32, S1024)

      .lowerFor({{S16, V2S16}});

      .clampScalar(BigTyIdx, S32, S1024);



    if (Op == G_MERGE_VALUES) {

      Builder.widenScalarIf(

llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir

+31 −12
Original line number Diff line number Diff line
@@ -2,23 +2,42 @@ 
# RUN: llc -march=aarch64 -O0 -run-pass=legalizer %s -o -  | FileCheck %s



---

name:  test_unmerge_s4

name:  test_unmerge_s4_constant

body: |

  bb.0:

    ; CHECK-LABEL: name: test_unmerge_s4

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4

    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)

    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)

    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)

    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)

    ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](s16)

    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s8)

    ; CHECK: $x0 = COPY [[ANYEXT]](s64)

    ; CHECK-LABEL: name: test_unmerge_s4_constant

    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0

    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

    ; CHECK: $x0 = COPY [[C1]](s64)

    %0:_(s8) = G_CONSTANT i8 0

    %1:_(s4), %2:_(s4)= G_UNMERGE_VALUES %0

    %3:_(s64) = G_ANYEXT %1

    $x0 = COPY %3



...



---

name:  test_unmerge_s4

body: |

  bb.0:

    liveins: $w0

    ; CHECK-LABEL: name: test_unmerge_s4

    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4

    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255

    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)

    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]

    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)

    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)

    ; CHECK: $x0 = COPY [[ANYEXT]](s64)

    ; CHECK: $x1 = COPY [[ANYEXT1]](s64)

    %0:_(s32) = COPY $w0

    %1:_(s8) = G_TRUNC %0

    %2:_(s4), %3:_(s4)= G_UNMERGE_VALUES %1

    %4:_(s64) = G_ANYEXT %2

    %5:_(s64) = G_ANYEXT %3

    $x0 = COPY %4

    $x1 = COPY %5



...

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir

+9 −7
Original line number Diff line number Diff line
@@ -427,14 +427,16 @@ body: | 
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1

    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3

    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)

    ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)

    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)

    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)

    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[UV2]](s32)

    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[UV3]](s32)

    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ANYEXT]](s64), [[ANYEXT1]](s64), [[ANYEXT2]](s64), [[ANYEXT3]](s64)

    ; CHECK: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16), [[UV14:%[0-9]+]]:_(s16), [[UV15:%[0-9]+]]:_(s16), [[UV16:%[0-9]+]]:_(s16), [[UV17:%[0-9]+]]:_(s16), [[UV18:%[0-9]+]]:_(s16), [[UV19:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s64>)

    ; CHECK: S_ENDPGM 0, implicit [[UV4]](s16), implicit [[UV5]](s16), implicit [[UV6]](s16), implicit [[UV7]](s16)

    ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)

    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)

    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)

    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)

    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16)

    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1

    %1:_(<2 x s32>) = COPY $vgpr2_vgpr3

    %2:_(<4 x s32>) = G_CONCAT_VECTORS %0, %1

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir

+47 −49
Original line number Diff line number Diff line
@@ -545,50 +545,45 @@ body: | 


    ; CHECK-LABEL: name: test_anyext_s32_to_s88

    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8

    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)

    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SHL]]

    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

    ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C1]](s32)

    ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]]

    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24

    ; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C2]](s32)

    ; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[SHL2]]

    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR2]](s64)

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)

    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

    ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8

    ; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)

    ; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)

    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

    ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255

    ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[UV]](s16)

    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C3]]

    ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[UV1]](s16)

    ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]

    ; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8

    ; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)

    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL3]]

    ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[UV2]](s16)

    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]

    ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[UV3]](s16)

    ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C3]]

    ; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)

    ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)

    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]

    ; CHECK: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16)

    ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL5]]

    ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[OR5]](s16)

    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)

    ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)

    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT2]], [[C1]](s32)

    ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT1]], [[SHL6]]

    ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)

    ; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[COPY5]](s16)

    ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT4]], [[C1]](s32)

    ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT3]], [[SHL7]]

    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32)

    ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255

    ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)

    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C2]]

    ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)

    ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C2]]

    ; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)

    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]

    ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)

    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C2]]

    ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)

    ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C2]]

    ; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)

    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]

    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)

    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]

    ; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C1]](s16)

    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]

    ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)

    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)

    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)

    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)

    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]

    ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)

    ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[COPY5]](s16)

    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)

    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]

    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR3]](s32), [[OR4]](s32)

    ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF

    ; CHECK: [[MV1:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64)

    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)

    ; CHECK: S_ENDPGM 0, implicit [[TRUNC1]](s88)

    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)

    ; CHECK: S_ENDPGM 0, implicit [[TRUNC3]](s88)

    %0:_(s32) = COPY $vgpr0

    %1:_(s88) = G_ANYEXT %0

    S_ENDPGM 0, implicit %1
@@ -616,15 +611,18 @@ body: | 


    ; CHECK-LABEL: name: test_anyext_s2_to_s112

    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)

    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)

    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]

    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)

    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL1]]

    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)

    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)

    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]

    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]

    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)

    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]

    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)

    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]

    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)

    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF

    ; CHECK: [[MV1:%[0-9]+]]:_(s448) = G_MERGE_VALUES [[MV]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64)