Unverified Commit 26ce3e42 authored by Yingwei Zheng's avatar Yingwei Zheng Committed by GitHub
Browse files

[InstCombine] Preserve NSW flags for `lshr (mul nuw X, C1), C2 -> mul nuw nsw... 

[InstCombine] Preserve NSW flags for `lshr (mul nuw X, C1), C2 -> mul nuw nsw X, (C1 >> C2)` (#72625)

Alive2: https://alive2.llvm.org/ce/z/TU_V9M

This missed optimization is discovered with the help of
https://github.com/AliveToolkit/alive2/pull/962.
parent f049395f

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

+4 −3
Original line number Diff line number Diff line
@@ -1435,12 +1435,13 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) { 
      if (Op0->hasOneUse()) {

        APInt NewMulC = MulC->lshr(ShAmtC);

        // if c is divisible by (1 << ShAmtC):

        // lshr (mul nuw x, MulC), ShAmtC -> mul nuw x, (MulC >> ShAmtC)

        // lshr (mul nuw x, MulC), ShAmtC -> mul nuw nsw x, (MulC >> ShAmtC)

        if (MulC->eq(NewMulC.shl(ShAmtC))) {

          auto *NewMul =

              BinaryOperator::CreateNUWMul(X, ConstantInt::get(Ty, NewMulC));

          BinaryOperator *OrigMul = cast<BinaryOperator>(Op0);

          NewMul->setHasNoSignedWrap(OrigMul->hasNoSignedWrap());

          assert(ShAmtC != 0 &&

                 "lshr X, 0 should be handled by simplifyLShrInst.");

          NewMul->setHasNoSignedWrap(true);

          return NewMul;

        }

      }

llvm/test/Transforms/InstCombine/shift-logic.ll

+2 −2
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ define i32 @PR44028(i32 %x) { 


define i64 @lshr_mul(i64 %0) {

; CHECK-LABEL: @lshr_mul(

; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP0:%.*]], 13

; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw nsw i64 [[TMP0:%.*]], 13

; CHECK-NEXT:    ret i64 [[TMP2]]

;

  %2 = mul nuw i64 %0, 52
@@ -279,7 +279,7 @@ define i64 @lshr_mul_nuw_nsw(i64 %0) { 


define <4 x i32> @lshr_mul_vector(<4 x i32> %0) {

; CHECK-LABEL: @lshr_mul_vector(

; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw <4 x i32> [[TMP0:%.*]], <i32 13, i32 13, i32 13, i32 13>

; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw nsw <4 x i32> [[TMP0:%.*]], <i32 13, i32 13, i32 13, i32 13>

; CHECK-NEXT:    ret <4 x i32> [[TMP2]]

;

  %2 = mul nuw <4 x i32> %0, <i32 52, i32 52, i32 52, i32 52>