Commit 2291bd13 authored by Austin Kerbow's avatar Austin Kerbow
Browse files

[AMDGPU] Update subtarget features for new target ID support 

Support for XNACK and SRAMECC is not static on some GPUs. We must be able
to differentiate between different scenarios for these dynamic subtarget
features.

The possible settings are:

- Unsupported: The GPU has no support for XNACK/SRAMECC.
- Any: Preference is unspecified. Use conservative settings that can run anywhere.
- Off: Request support for XNACK/SRAMECC Off
- On: Request support for XNACK/SRAMECC On

GCNSubtarget will track the four options based on the following criteria. If
the subtarget does not support XNACK/SRAMECC we say the setting is
"Unsupported". If no subtarget features for XNACK/SRAMECC are requested we
must support "Any" mode. If the subtarget features XNACK/SRAMECC exist in the
feature string when initializing the subtarget, the settings are "On/Off".

The defaults are updated to be conservatively correct, meaning if no setting
for XNACK or SRAMECC is explicitly requested, defaults will be used which
generate code that can be run anywhere. This corresponds to the "Any" setting.

Differential Revision: https://reviews.llvm.org/D85882
parent 683719bc

llvm/lib/Target/AMDGPU/AMDGPU.td

+34 −59
Original line number Diff line number Diff line
@@ -129,10 +129,10 @@ def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts", 
  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"

>;



def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",

  "DoesNotSupportXNACK",

def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",

  "SupportsXNACK",

  "true",

  "Hardware does not support XNACK"

  "Hardware supports XNACK"

>;



// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
@@ -491,13 +491,13 @@ def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts", 
  [FeatureFlatGlobalInsts]

>;



def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",

  "DoesNotSupportSRAMECC",

def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",

  "SupportsSRAMECC",

  "true",

  "Hardware does not support SRAM ECC"

  "Hardware supports SRAMECC"

>;



def FeatureSRAMECC : SubtargetFeature<"sram-ecc",

def FeatureSRAMECC : SubtargetFeature<"sramecc",

  "EnableSRAMECC",

  "true",

  "Enable SRAMECC"
@@ -675,8 +675,7 @@ def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", 
  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,

  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,

  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,

  FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,

  FeatureDoesNotSupportXNACK]

  FeatureTrigReducedRange]

>;



def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
@@ -685,8 +684,7 @@ def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", 
  FeatureWavefrontSize64, FeatureFlatAddressSpace,

  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,

  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,

  FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC,

  FeatureUnalignedBufferAccess]

  FeatureDsSrc2Insts, FeatureUnalignedBufferAccess]

>;



def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
@@ -699,9 +697,7 @@ def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", 
   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,

   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,

   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,

   FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32,

   FeatureUnalignedBufferAccess

  ]

   FeatureDsSrc2Insts, FeatureFastDenormalF32, FeatureUnalignedBufferAccess]

>;



def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
@@ -717,9 +713,8 @@ def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9", 
   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,

   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,

   FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts,

   FeatureFastDenormalF32, FeatureUnalignedBufferAccess,

   FeatureUnalignedDSAccess

  ]

   FeatureFastDenormalF32, FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,

   FeatureSupportsXNACK]

>;



def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
@@ -735,7 +730,7 @@ def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10", 
   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,

   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,

   FeatureVOP3Literal, FeatureDPP8,

   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,

   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,

   FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16,

   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess

  ]
@@ -748,84 +743,72 @@ class FeatureSet<list<SubtargetFeature> Features_> { 
def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,

   FeatureFastFMAF32,

   HalfRate64Ops,

   FeatureLDSBankCount32,

   FeatureDoesNotSupportXNACK]>;

   FeatureLDSBankCount32]>;



def FeatureISAVersion6_0_1 : FeatureSet<

  [FeatureSouthernIslands,

   FeatureLDSBankCount32,

   FeatureDoesNotSupportXNACK]>;

   FeatureLDSBankCount32]>;



def FeatureISAVersion6_0_2 : FeatureSet<

  [FeatureSouthernIslands,

   FeatureLDSBankCount32,

   FeatureDoesNotSupportXNACK]>;

   FeatureLDSBankCount32]>;



def FeatureISAVersion7_0_0 : FeatureSet<

  [FeatureSeaIslands,

   FeatureLDSBankCount32,

   FeatureDoesNotSupportXNACK]>;

   FeatureLDSBankCount32]>;



def FeatureISAVersion7_0_1 : FeatureSet<

  [FeatureSeaIslands,

   HalfRate64Ops,

   FeatureLDSBankCount32,

   FeatureFastFMAF32,

   FeatureDoesNotSupportXNACK]>;

   FeatureFastFMAF32]>;



def FeatureISAVersion7_0_2 : FeatureSet<

  [FeatureSeaIslands,

   FeatureLDSBankCount16,

   FeatureFastFMAF32,

   FeatureDoesNotSupportXNACK]>;

   FeatureFastFMAF32]>;



def FeatureISAVersion7_0_3 : FeatureSet<

  [FeatureSeaIslands,

   FeatureLDSBankCount16,

   FeatureDoesNotSupportXNACK]>;

   FeatureLDSBankCount16]>;



def FeatureISAVersion7_0_4 : FeatureSet<

  [FeatureSeaIslands,

   FeatureLDSBankCount32,

   FeatureDoesNotSupportXNACK]>;

   FeatureLDSBankCount32]>;



def FeatureISAVersion7_0_5 : FeatureSet<

  [FeatureSeaIslands,

   FeatureLDSBankCount16,

   FeatureDoesNotSupportXNACK]>;

   FeatureLDSBankCount16]>;



def FeatureISAVersion8_0_1 : FeatureSet<

  [FeatureVolcanicIslands,

   FeatureFastFMAF32,

   HalfRate64Ops,

   FeatureLDSBankCount32,

   FeatureXNACK,

   FeatureSupportsXNACK,

   FeatureUnpackedD16VMem]>;



def FeatureISAVersion8_0_2 : FeatureSet<

  [FeatureVolcanicIslands,

   FeatureLDSBankCount32,

   FeatureSGPRInitBug,

   FeatureUnpackedD16VMem,

   FeatureDoesNotSupportXNACK]>;

   FeatureUnpackedD16VMem]>;



def FeatureISAVersion8_0_3 : FeatureSet<

  [FeatureVolcanicIslands,

   FeatureLDSBankCount32,

   FeatureUnpackedD16VMem,

   FeatureDoesNotSupportXNACK]>;

   FeatureUnpackedD16VMem]>;



def FeatureISAVersion8_0_5 : FeatureSet<

  [FeatureVolcanicIslands,

   FeatureLDSBankCount32,

   FeatureSGPRInitBug,

   FeatureUnpackedD16VMem,

   FeatureDoesNotSupportXNACK]>;

   FeatureUnpackedD16VMem]>;



def FeatureISAVersion8_1_0 : FeatureSet<

  [FeatureVolcanicIslands,

   FeatureLDSBankCount16,

   FeatureXNACK,

   FeatureSupportsXNACK,

   FeatureImageStoreD16Bug,

   FeatureImageGather4D16Bug]>;
@@ -833,24 +816,18 @@ def FeatureISAVersion9_0_0 : FeatureSet< 
  [FeatureGFX9,

   FeatureMadMixInsts,

   FeatureLDSBankCount32,

   FeatureDoesNotSupportXNACK,

   FeatureDoesNotSupportSRAMECC,

   FeatureImageGather4D16Bug]>;



def FeatureISAVersion9_0_2 : FeatureSet<

  [FeatureGFX9,

   FeatureMadMixInsts,

   FeatureLDSBankCount32,

   FeatureXNACK,

   FeatureDoesNotSupportSRAMECC,

   FeatureImageGather4D16Bug]>;



def FeatureISAVersion9_0_4 : FeatureSet<

  [FeatureGFX9,

   FeatureLDSBankCount32,

   FeatureFmaMixInsts,

   FeatureDoesNotSupportXNACK,

   FeatureDoesNotSupportSRAMECC,

   FeatureImageGather4D16Bug]>;



def FeatureISAVersion9_0_6 : FeatureSet<
@@ -861,7 +838,7 @@ def FeatureISAVersion9_0_6 : FeatureSet< 
   FeatureDLInsts,

   FeatureDot1Insts,

   FeatureDot2Insts,

   FeatureDoesNotSupportXNACK,

   FeatureSupportsSRAMECC,

   FeatureImageGather4D16Bug]>;



def FeatureISAVersion9_0_8 : FeatureSet<
@@ -879,7 +856,7 @@ def FeatureISAVersion9_0_8 : FeatureSet< 
   FeatureMAIInsts,

   FeaturePkFmacF16Inst,

   FeatureAtomicFaddInsts,

   FeatureSRAMECC,

   FeatureSupportsSRAMECC,

   FeatureMFMAInlineLiteralBug,

   FeatureImageGather4D16Bug]>;
@@ -887,7 +864,6 @@ def FeatureISAVersion9_0_9 : FeatureSet< 
  [FeatureGFX9,

   FeatureMadMixInsts,

   FeatureLDSBankCount32,

   FeatureXNACK,

   FeatureImageGather4D16Bug]>;



def FeatureISAVersion9_0_C : FeatureSet<
@@ -928,7 +904,7 @@ def FeatureISAVersion10_1_0 : FeatureSet< 
     FeatureMadMacF32Insts,

     FeatureDsSrc2Insts,

     FeatureLdsMisalignedBug,

     FeatureDoesNotSupportXNACK])>;

     FeatureSupportsXNACK])>;



def FeatureISAVersion10_1_1 : FeatureSet<

  !listconcat(FeatureGroup.GFX10_1_Bugs,
@@ -949,7 +925,7 @@ def FeatureISAVersion10_1_1 : FeatureSet< 
     FeatureMadMacF32Insts,

     FeatureDsSrc2Insts,

     FeatureLdsMisalignedBug,

     FeatureDoesNotSupportXNACK])>;

     FeatureSupportsXNACK])>;



def FeatureISAVersion10_1_2 : FeatureSet<

  !listconcat(FeatureGroup.GFX10_1_Bugs,
@@ -970,7 +946,7 @@ def FeatureISAVersion10_1_2 : FeatureSet< 
     FeatureMadMacF32Insts,

     FeatureDsSrc2Insts,

     FeatureLdsMisalignedBug,

     FeatureDoesNotSupportXNACK])>;

     FeatureSupportsXNACK])>;



def FeatureISAVersion10_3_0 : FeatureSet<

  [FeatureGFX10,
@@ -983,8 +959,7 @@ def FeatureISAVersion10_3_0 : FeatureSet< 
   FeatureDot5Insts,

   FeatureDot6Insts,

   FeatureNSAEncoding,

   FeatureWavefrontSize32,

   FeatureDoesNotSupportXNACK]>;

   FeatureWavefrontSize32]>;



//===----------------------------------------------------------------------===//

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

+10 −17
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include "AMDGPURegisterBankInfo.h"

#include "AMDGPUTargetMachine.h"

#include "SIMachineFunctionInfo.h"

#include "Utils/AMDGPUBaseInfo.h"

#include "llvm/ADT/SmallString.h"

#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"

#include "llvm/CodeGen/MachineScheduler.h"
@@ -88,8 +89,7 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, 
  // Similarly we want enable-prt-strict-null to be on by default and not to

  // unset everything else if it is disabled



  // Assuming ECC is enabled is the conservative default.

  SmallString<256> FullFS("+promote-alloca,+load-store-opt,+enable-ds128,+sram-ecc,+xnack,");

  SmallString<256> FullFS("+promote-alloca,+load-store-opt,+enable-ds128,");



  // Turn on features that HSA ABI requires. Also turn on FlatForGlobal by default

  if (isAmdHsaOS())
@@ -164,20 +164,12 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, 


  HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;



  // Disable XNACK on targets where it is not enabled by default unless it is

  // explicitly requested.

  if (!FS.contains("+xnack") && DoesNotSupportXNACK && EnableXNACK) {

    ToggleFeature(AMDGPU::FeatureXNACK);

    EnableXNACK = false;

  }

  TargetID.setTargetIDFromFeaturesString(FS);



  // ECC is on by default, but turn it off if the hardware doesn't support it

  // anyway. This matters for the gfx9 targets with d16 loads, but don't support

  // ECC.

  if (DoesNotSupportSRAMECC && EnableSRAMECC) {

    ToggleFeature(AMDGPU::FeatureSRAMECC);

    EnableSRAMECC = false;

  }

  LLVM_DEBUG(dbgs() << "xnack setting for subtarget: "

                    << TargetID.getXnackSetting() << '\n');

  LLVM_DEBUG(dbgs() << "sramecc setting for subtarget: "

                    << TargetID.getSramEccSetting() << '\n');



  return *this;

}
@@ -206,6 +198,7 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, 
    AMDGPUGenSubtargetInfo(TT, GPU, /*TuneCPU*/ GPU, FS),

    AMDGPUSubtarget(TT),

    TargetTriple(TT),

    TargetID(*this),

    Gen(INVALID),

    InstrItins(getInstrItineraryForCPU(GPU)),

    LDSBankCount(0),
@@ -221,8 +214,8 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, 
    UnalignedAccessMode(false),



    HasApertureRegs(false),

    SupportsXNACK(false),

    EnableXNACK(false),

    DoesNotSupportXNACK(false),

    EnableCuMode(false),

    TrapHandler(false),
@@ -271,8 +264,8 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, 
    HasMAIInsts(false),

    HasPkFmacF16Inst(false),

    HasAtomicFaddInsts(false),

    SupportsSRAMECC(false),

    EnableSRAMECC(false),

    DoesNotSupportSRAMECC(false),

    HasNoSdstCMPX(false),

    HasVscnt(false),

    HasGetWaveIdInst(false),

llvm/lib/Target/AMDGPU/GCNSubtarget.h

+13 −8
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ private: 
protected:

  // Basic subtarget description.

  Triple TargetTriple;

  AMDGPU::IsaInfo::AMDGPUTargetID TargetID;

  unsigned Gen;

  InstrItineraryData InstrItins;

  int LDSBankCount;
@@ -88,8 +89,12 @@ protected: 
  bool UnalignedScratchAccess;

  bool UnalignedAccessMode;

  bool HasApertureRegs;

  bool SupportsXNACK;



  // This should not be used directly. 'TargetID' tracks the dynamic settings

  // for XNACK.

  bool EnableXNACK;

  bool DoesNotSupportXNACK;



  bool EnableCuMode;

  bool TrapHandler;
@@ -142,8 +147,12 @@ protected: 
  bool HasMAIInsts;

  bool HasPkFmacF16Inst;

  bool HasAtomicFaddInsts;

  bool SupportsSRAMECC;



  // This should not be used directly. 'TargetID' tracks the dynamic settings

  // for SRAMECC.

  bool EnableSRAMECC;

  bool DoesNotSupportSRAMECC;



  bool HasNoSdstCMPX;

  bool HasVscnt;

  bool HasGetWaveIdInst;
@@ -498,7 +507,7 @@ public: 
  }



  bool isXNACKEnabled() const {

    return EnableXNACK;

    return TargetID.isXnackOnOrAny();

  }



  bool isCuModeEnabled() const {
@@ -561,7 +570,7 @@ public: 
  }



  bool d16PreservesUnusedBits() const {

    return hasD16LoadStore() && !isSRAMECCEnabled();

    return hasD16LoadStore() && !TargetID.isSramEccOnOrAny();

  }



  bool hasD16Images() const {
@@ -669,10 +678,6 @@ public: 
    return HasAtomicFaddInsts;

  }



  bool isSRAMECCEnabled() const {

    return EnableSRAMECC;

  }



  bool hasNoSdstCMPX() const {

    return HasNoSdstCMPX;

  }

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

+109 −1
Original line number Diff line number Diff line
@@ -246,6 +246,94 @@ int getMCOpcode(uint16_t Opcode, unsigned Gen) { 


namespace IsaInfo {



AMDGPUTargetID::AMDGPUTargetID(const MCSubtargetInfo &STI)

    : XnackSetting(TargetIDSetting::Any), SramEccSetting(TargetIDSetting::Any) {

  if (!STI.getFeatureBits().test(FeatureSupportsXNACK))

    XnackSetting = TargetIDSetting::Unsupported;

  if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))

    SramEccSetting = TargetIDSetting::Unsupported;

}



void AMDGPUTargetID::setTargetIDFromFeaturesString(StringRef FS) {

  // Check if xnack or sramecc is explicitly enabled or disabled.  In the

  // absence of the target features we assume we must generate code that can run

  // in any environment.

  SubtargetFeatures Features(FS);

  Optional<bool> XnackRequested;

  Optional<bool> SramEccRequested;



  for (const std::string &Feature : Features.getFeatures()) {

    if (Feature == "+xnack")

      XnackRequested = true;

    else if (Feature == "-xnack")

      XnackRequested = false;

    else if (Feature == "+sramecc")

      SramEccRequested = true;

    else if (Feature == "-sramecc")

      SramEccRequested = false;

  }



  bool XnackSupported = isXnackSupported();

  bool SramEccSupported = isSramEccSupported();



  if (XnackRequested) {

    if (XnackSupported) {

      XnackSetting =

          *XnackRequested ? TargetIDSetting::On : TargetIDSetting::Off;

    } else {

      // If a specific xnack setting was requested and this GPU does not support

      // xnack emit a warning. Setting will remain set to "Unsupported".

      if (*XnackRequested) {

        errs() << "warning: xnack 'On' was requested for a processor that does "

                  "not support it!\n";

      } else {

        errs() << "warning: xnack 'Off' was requested for a processor that "

                  "does not support it!\n";

      }

    }

  }



  if (SramEccRequested) {

    if (SramEccSupported) {

      SramEccSetting =

          *SramEccRequested ? TargetIDSetting::On : TargetIDSetting::Off;

    } else {

      // If a specific sramecc setting was requested and this GPU does not

      // support sramecc emit a warning. Setting will remain set to

      // "Unsupported".

      if (*SramEccRequested) {

        errs() << "warning: sramecc 'On' was requested for a processor that "

                  "does not support it!\n";

      } else {

        errs() << "warning: sramecc 'Off' was requested for a processor that "

                  "does not support it!\n";

      }

    }

  }

}



static TargetIDSetting

getTargetIDSettingFromFeatureString(StringRef FeatureString) {

  if (FeatureString.endswith("-"))

    return TargetIDSetting::Off;

  if (FeatureString.endswith("+"))

    return TargetIDSetting::On;



  llvm_unreachable("Malformed feature string");

}



void AMDGPUTargetID::setTargetIDFromTargetIDStream(StringRef TargetID) {

  SmallVector<StringRef, 3> TargetIDSplit;

  TargetID.split(TargetIDSplit, ':');



  for (const auto &FeatureString : TargetIDSplit) {

    if (FeatureString.startswith("xnack"))

      XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);

    if (FeatureString.startswith("sramecc"))

      SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);

  }

}



void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {

  auto TargetTriple = STI->getTargetTriple();

  auto Version = getIsaVersion(STI->getCPU());
@@ -262,7 +350,7 @@ void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) { 
  if (hasXNACK(*STI))

    Stream << "+xnack";

  if (hasSRAMECC(*STI))

    Stream << "+sram-ecc";

    Stream << "+sramecc";



  Stream.flush();

}
@@ -1688,4 +1776,24 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format, 
}



} // namespace AMDGPU



raw_ostream &operator<<(raw_ostream &OS,

                        const AMDGPU::IsaInfo::TargetIDSetting S) {

  switch (S) {

  case (AMDGPU::IsaInfo::TargetIDSetting::Unsupported):

    OS << "Unsupported";

    break;

  case (AMDGPU::IsaInfo::TargetIDSetting::Any):

    OS << "Any";

    break;

  case (AMDGPU::IsaInfo::TargetIDSetting::Off):

    OS << "Off";

    break;

  case (AMDGPU::IsaInfo::TargetIDSetting::On):

    OS << "On";

    break;

  }

  return OS;

}



} // namespace llvm

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

+82 −0
Original line number Diff line number Diff line
@@ -69,6 +69,84 @@ enum { 
  TRAP_NUM_SGPRS = 16

};



enum class TargetIDSetting {

  Unsupported,

  Any,

  Off,

  On

};



class AMDGPUTargetID {

private:

  TargetIDSetting XnackSetting;

  TargetIDSetting SramEccSetting;



public:

  explicit AMDGPUTargetID(const MCSubtargetInfo &STI);

  ~AMDGPUTargetID() = default;



  /// \return True if the current xnack setting is not "Unsupported".

  bool isXnackSupported() const {

    return XnackSetting != TargetIDSetting::Unsupported;

  }



  /// \returns True if the current xnack setting is "On" or "Any".

  bool isXnackOnOrAny() const {

    return XnackSetting == TargetIDSetting::On ||

        XnackSetting == TargetIDSetting::Any;

  }



  /// \returns True if current xnack setting is "On" or "Off",

  /// false otherwise.

  bool isXnackOnOrOff() const {

    return getXnackSetting() == TargetIDSetting::On ||

        getXnackSetting() == TargetIDSetting::Off;

  }



  /// \returns The current xnack TargetIDSetting, possible options are

  /// "Unsupported", "Any", "Off", and "On".

  TargetIDSetting getXnackSetting() const {

    return XnackSetting;

  }



  /// Sets xnack setting to \p NewXnackSetting.

  void setXnackSetting(TargetIDSetting NewXnackSetting) {

    XnackSetting = NewXnackSetting;

  }



  /// \return True if the current sramecc setting is not "Unsupported".

  bool isSramEccSupported() const {

    return SramEccSetting != TargetIDSetting::Unsupported;

  }



  /// \returns True if the current sramecc setting is "On" or "Any".

  bool isSramEccOnOrAny() const {

  return SramEccSetting == TargetIDSetting::On ||

      SramEccSetting == TargetIDSetting::Any;

  }



  /// \returns True if current sramecc setting is "On" or "Off",

  /// false otherwise.

  bool isSramEccOnOrOff() const {

    return getSramEccSetting() == TargetIDSetting::On ||

        getSramEccSetting() == TargetIDSetting::Off;

  }



  /// \returns The current sramecc TargetIDSetting, possible options are

  /// "Unsupported", "Any", "Off", and "On".

  TargetIDSetting getSramEccSetting() const {

    return SramEccSetting;

  }



  /// Sets sramecc setting to \p NewSramEccSetting.

  void setSramEccSetting(TargetIDSetting NewSramEccSetting) {

    SramEccSetting = NewSramEccSetting;

  }



  void setTargetIDFromFeaturesString(StringRef FS);

  void setTargetIDFromTargetIDStream(StringRef TargetID);

};



/// Streams isa version string for given subtarget \p STI into \p Stream.

void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
@@ -873,6 +951,10 @@ struct SIModeRegisterDefaults { 
};



} // end namespace AMDGPU



raw_ostream &operator<<(raw_ostream &OS,

                        const AMDGPU::IsaInfo::TargetIDSetting S);



} // end namespace llvm



#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H