Commit 1f0d24ce authored by Matt Arsenault's avatar Matt Arsenault
Browse files

update_llc_test_checks: Fix broken amdgpu test 

Use the correct address space for alloca. Also use opaque pointers.
parent 82b94a9f

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll

+8 −8
Original line number Diff line number Diff line 
; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s



define i64 @i64_test(i64 %i) nounwind readnone {

  %loc = alloca i64

  %j = load i64, i64 * %loc

  %loc = alloca i64, addrspace(5)

  %j = load i64, ptr addrspace(5) %loc

  %r = add i64 %i, %j

  ret i64 %r

}



define i64 @i32_test(i32 %i) nounwind readnone {

  %loc = alloca i32

  %j = load i32, i32 * %loc

  %loc = alloca i32, addrspace(5)

  %j = load i32, ptr addrspace(5) %loc

  %r = add i32 %i, %j

  %ext = zext i32 %r to i64

  ret i64 %ext

}



define i64 @i16_test(i16 %i) nounwind readnone {

  %loc = alloca i16

  %j = load i16, i16 * %loc

  %loc = alloca i16, addrspace(5)

  %j = load i16, ptr addrspace(5) %loc

  %r = add i16 %i, %j

  %ext = zext i16 %r to i64

  ret i64 %ext

}



define i64 @i8_test(i8 %i) nounwind readnone {

  %loc = alloca i8

  %j = load i8, i8 * %loc

  %loc = alloca i8, addrspace(5)

  %j = load i8, ptr addrspace(5) %loc

  %r = add i8 %i, %j

  %ext = zext i8 %r to i64

  ret i64 %ext

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected

+8 −8
Original line number Diff line number Diff line
@@ -10,8 +10,8 @@ define i64 @i64_test(i64 %i) nounwind readnone { 
; CHECK-NEXT:    t13: ch,glue = CopyToReg t11, Register:i32 $vgpr1, t17, t11:1

; CHECK-NEXT:    t14: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t13, t13:1

; CHECK-EMPTY:

  %loc = alloca i64

  %j = load i64, i64 * %loc

  %loc = alloca i64, addrspace(5)

  %j = load i64, ptr addrspace(5) %loc

  %r = add i64 %i, %j

  ret i64 %r

}
@@ -25,8 +25,8 @@ define i64 @i32_test(i32 %i) nounwind readnone { 
; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1

; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1

; CHECK-EMPTY:

  %loc = alloca i32

  %j = load i32, i32 * %loc

  %loc = alloca i32, addrspace(5)

  %j = load i32, ptr addrspace(5) %loc

  %r = add i32 %i, %j

  %ext = zext i32 %r to i64

  ret i64 %ext
@@ -41,8 +41,8 @@ define i64 @i16_test(i16 %i) nounwind readnone { 
; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1

; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1

; CHECK-EMPTY:

  %loc = alloca i16

  %j = load i16, i16 * %loc

  %loc = alloca i16, addrspace(5)

  %j = load i16, ptr addrspace(5) %loc

  %r = add i16 %i, %j

  %ext = zext i16 %r to i64

  ret i64 %ext
@@ -57,8 +57,8 @@ define i64 @i8_test(i8 %i) nounwind readnone { 
; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1

; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1

; CHECK-EMPTY:

  %loc = alloca i8

  %j = load i8, i8 * %loc

  %loc = alloca i8, addrspace(5)

  %j = load i8, ptr addrspace(5) %loc

  %r = add i8 %i, %j

  %ext = zext i8 %r to i64

  ret i64 %ext