Commit 1f054d66 authored by Matt Arsenault's avatar Matt Arsenault Committed by Matt Arsenault
Browse files

AMDGPU/GlobalISel: Fix mapping and selection of llvm.amdgcn.div.fixup

parent ab8a7a29

llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td

+5 −1
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp, 
// Single or double precision division fixup.

// Special case divide fixup and flags(src0 = Quotient, src1 =

// Denominator, src2 = Numerator).

def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;

def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;



def AMDGPUfmad_ftz : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
@@ -434,6 +434,10 @@ def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2), 
  [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),

   (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;



def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),

  [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),

   (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;



def AMDGPUffbh_i32 : PatFrags<(ops node:$src),

  [(int_amdgcn_sffbh node:$src),

   (AMDGPUffbh_i32_impl node:$src)]>;

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

+1 −0
Original line number Diff line number Diff line
@@ -2580,6 +2580,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
    default:

      return getInvalidInstructionMapping();

    case Intrinsic::amdgcn_div_fmas:

    case Intrinsic::amdgcn_div_fixup:

    case Intrinsic::amdgcn_trig_preop:

    case Intrinsic::amdgcn_sin:

    case Intrinsic::amdgcn_cos: