Unverified Commit 1ed555a6 authored by Florian Hahn's avatar Florian Hahn
Browse files

[LV] Fix test cases where vector loop never executed. 

It looks like the vector loops in the modified test cases
unintentionally never get executed. Update the exit condition to ensure
it does to avoid them getting optimized away in upcoming changes.
parent 9f6c09de

llvm/test/Transforms/LoopVectorize/AArch64/extractvalue-no-scalarization-required.ll

+6 −6
Original line number Diff line number Diff line
@@ -32,8 +32,8 @@ 
; FORCED-NEXT:    %6 = bitcast i64* %5 to <2 x i64>*

; FORCED-NEXT:    store <2 x i64> %4, <2 x i64>* %6, align 4

; FORCED-NEXT:    %index.next = add nuw i32 %index, 2

; FORCED-NEXT:    %7 = icmp eq i32 %index.next, 0

; FORCED-NEXT:    br i1 %7, label %middle.block, label %vector.body, !llvm.loop !0

; FORCED-NEXT:    %7 = icmp eq i32 %index.next, 1000

; FORCED-NEXT:    br i1 %7, label %middle.block, label %vector.body



define void @test1(i64* %dst, {i64, i64} %sv) {

entry:
@@ -47,7 +47,7 @@ loop.body: 
  %add = add i64 %a, %b

  store i64 %add, i64* %addr

  %iv.next = add nsw i32 %iv, 1

  %cond = icmp ne i32 %iv.next, 0

  %cond = icmp ne i32 %iv.next, 1000

  br i1 %cond, label %loop.body, label %exit



exit:
@@ -82,8 +82,8 @@ declare float @powf(float, float) readnone nounwind 
; FORCED-NEXT:    %6 = bitcast float* %5 to <2 x float>*

; FORCED-NEXT:    store <2 x float> %4, <2 x float>* %6, align 4

; FORCED-NEXT:    %index.next = add nuw i32 %index, 2

; FORCED-NEXT:    %7 = icmp eq i32 %index.next, 0

; FORCED-NEXT:    br i1 %7, label %middle.block, label %vector.body, !llvm.loop !4

; FORCED-NEXT:    %7 = icmp eq i32 %index.next, 1000

; FORCED-NEXT:    br i1 %7, label %middle.block, label %vector.body



define void @test_getVectorCallCost(float* %dst, {float, float} %sv) {

entry:
@@ -97,7 +97,7 @@ loop.body: 
  %p = call float @powf(float %a, float %b)

  store float %p, float* %addr

  %iv.next = add nsw i32 %iv, 1

  %cond = icmp ne i32 %iv.next, 0

  %cond = icmp ne i32 %iv.next, 1000

  br i1 %cond, label %loop.body, label %exit



exit:

llvm/test/Transforms/LoopVectorize/instruction-only-used-outside-of-loop.ll

+18 −18
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
define i32 @one_direct_branch(i32* %src) {

; CHECK-LABEL: @one_direct_branch(

; CHECK-NEXT:  entry:

; CHECK-NEXT:    br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]

; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]

; CHECK:       vector.ph:

; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]

; CHECK:       vector.body:
@@ -17,14 +17,14 @@ define i32 @one_direct_branch(i32* %src) { 
; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP3]], align 4

; CHECK-NEXT:    [[TMP4:%.*]] = xor <4 x i32> <i32 25500, i32 25500, i32 25500, i32 25500>, [[WIDE_LOAD]]

; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4

; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 0

; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000

; CHECK-NEXT:    br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]

; CHECK:       middle.block:

; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3

; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 0, 0

; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 1000, 1000

; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]

; CHECK:       scalar.ph:

; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 0, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]

; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]

; CHECK-NEXT:    br label [[LOOP:%.*]]

; CHECK:       loop:

; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
@@ -35,7 +35,7 @@ define i32 @one_direct_branch(i32* %src) { 
; CHECK:       loop.latch:

; CHECK-NEXT:    [[PHI_XOR:%.*]] = phi i32 [ [[XOR]], [[LOOP]] ]

; CHECK-NEXT:    [[IV_NEXT]] = add nsw i32 [[IV]], 1

; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 0

; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 1000

; CHECK-NEXT:    br i1 [[TOBOOL_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]

; CHECK:       exit:

; CHECK-NEXT:    [[XOR_LCSSA:%.*]] = phi i32 [ [[PHI_XOR]], [[LOOP_LATCH]] ], [ [[TMP6]], [[MIDDLE_BLOCK]] ]
@@ -54,7 +54,7 @@ loop: 
loop.latch:

  %phi.xor = phi i32 [ %xor, %loop ]

  %iv.next = add nsw i32 %iv, 1

  %tobool.not = icmp eq i32 %iv.next, 0

  %tobool.not = icmp eq i32 %iv.next, 1000

  br i1 %tobool.not, label %exit, label %loop



exit:
@@ -65,7 +65,7 @@ exit: 
define i32 @two_direct_branch(i32* %src) {

; CHECK-LABEL: @two_direct_branch(

; CHECK-NEXT:  entry:

; CHECK-NEXT:    br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]

; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]

; CHECK:       vector.ph:

; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]

; CHECK:       vector.body:
@@ -77,14 +77,14 @@ define i32 @two_direct_branch(i32* %src) { 
; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP3]], align 4

; CHECK-NEXT:    [[TMP4:%.*]] = xor <4 x i32> <i32 25500, i32 25500, i32 25500, i32 25500>, [[WIDE_LOAD]]

; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4

; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 0

; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000

; CHECK-NEXT:    br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]

; CHECK:       middle.block:

; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3

; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 0, 0

; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 1000, 1000

; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]

; CHECK:       scalar.ph:

; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 0, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]

; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]

; CHECK-NEXT:    br label [[LOOP:%.*]]

; CHECK:       loop:

; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
@@ -98,7 +98,7 @@ define i32 @two_direct_branch(i32* %src) { 
; CHECK:       loop.latch:

; CHECK-NEXT:    [[PHI_XOR:%.*]] = phi i32 [ [[PHI_XOR_1]], [[BB]] ]

; CHECK-NEXT:    [[IV_NEXT]] = add nsw i32 [[IV]], 1

; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 0

; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 1000

; CHECK-NEXT:    br i1 [[TOBOOL_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]

; CHECK:       exit:

; CHECK-NEXT:    [[XOR_LCSSA:%.*]] = phi i32 [ [[PHI_XOR]], [[LOOP_LATCH]] ], [ [[TMP6]], [[MIDDLE_BLOCK]] ]
@@ -121,7 +121,7 @@ bb: 
loop.latch:

  %phi.xor = phi i32 [ %phi.xor.1, %bb ]

  %iv.next = add nsw i32 %iv, 1

  %tobool.not = icmp eq i32 %iv.next, 0

  %tobool.not = icmp eq i32 %iv.next, 1000

  br i1 %tobool.not, label %exit, label %loop



exit:
@@ -132,7 +132,7 @@ exit: 
define i32 @cond_branch(i32 %a, i32* %src) {

; CHECK-LABEL: @cond_branch(

; CHECK-NEXT:  entry:

; CHECK-NEXT:    br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]

; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]

; CHECK:       vector.ph:

; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i32 0

; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
@@ -151,14 +151,14 @@ define i32 @cond_branch(i32 %a, i32* %src) { 
; CHECK-NEXT:    [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> <i32 10, i32 10, i32 10, i32 10>, <4 x i32> [[TMP4]]

; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4

; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4>

; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 0

; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000

; CHECK-NEXT:    br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]

; CHECK:       middle.block:

; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3

; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 0, 0

; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 1000, 1000

; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]

; CHECK:       scalar.ph:

; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 0, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]

; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]

; CHECK-NEXT:    br label [[LOOP:%.*]]

; CHECK:       loop:

; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
@@ -172,7 +172,7 @@ define i32 @cond_branch(i32 %a, i32* %src) { 
; CHECK:       loop.latch:

; CHECK-NEXT:    [[PHI_XOR:%.*]] = phi i32 [ [[XOR]], [[LOOP]] ], [ 10, [[THEN]] ]

; CHECK-NEXT:    [[IV_NEXT]] = add nsw i32 [[IV]], 1

; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 0

; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 1000

; CHECK-NEXT:    br i1 [[TOBOOL_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]

; CHECK:       exit:

; CHECK-NEXT:    [[XOR_LCSSA:%.*]] = phi i32 [ [[PHI_XOR]], [[LOOP_LATCH]] ], [ [[TMP8]], [[MIDDLE_BLOCK]] ]
@@ -195,7 +195,7 @@ then: 
loop.latch:

  %phi.xor = phi i32 [ %xor, %loop ], [ 10, %then ]

  %iv.next = add nsw i32 %iv, 1

  %tobool.not = icmp eq i32 %iv.next, 0

  %tobool.not = icmp eq i32 %iv.next, 1000

  br i1 %tobool.not, label %exit, label %loop



exit: