Commit 1bf00219 authored by Jay Foad's avatar Jay Foad
Browse files

[AMDGPU] Handle multiple base operands in areMemAccessesTriviallyDisjoint 

Summary:
This is in preparation for getMemOperandsWithOffset returning more base
operands.

Depends on D73455.

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73456
parent 6461eadf

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+12 −16
Original line number Diff line number Diff line
@@ -2633,26 +2633,22 @@ static bool offsetsDoNotOverlap(int WidthA, int OffsetA, 


bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,

                                               const MachineInstr &MIb) const {

  const MachineOperand *BaseOp0, *BaseOp1;

  SmallVector<const MachineOperand *, 4> BaseOps0, BaseOps1;

  int64_t Offset0, Offset1;

  if (!getMemOperandsWithOffset(MIa, BaseOps0, Offset0, &RI) ||

      !getMemOperandsWithOffset(MIb, BaseOps1, Offset1, &RI))

    return false;



  if (getMemOperandWithOffset(MIa, BaseOp0, Offset0, &RI) &&

      getMemOperandWithOffset(MIb, BaseOp1, Offset1, &RI)) {

    if (!BaseOp0->isIdenticalTo(*BaseOp1))

  if (!memOpsHaveSameBaseOperands(BaseOps0, BaseOps1))

    return false;



  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {

    // FIXME: Handle ds_read2 / ds_write2.

    return false;

  }

    unsigned Width0 = (*MIa.memoperands_begin())->getSize();

    unsigned Width1 = (*MIb.memoperands_begin())->getSize();

    if (offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {

      return true;

    }

  }



  return false;

  unsigned Width0 = MIa.memoperands().front()->getSize();

  unsigned Width1 = MIb.memoperands().front()->getSize();

  return offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1);

}



bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,