Commit 1bacdcf4 authored by Stanislav Mekhanoshin's avatar Stanislav Mekhanoshin
Browse files

Extend LaneBitmask to 64 bit 

This is needed for D74873, AMDGPU going to have 16 bit subregs
and the largest tuple is 32 VGPRs, which results in 64 lanes.

Differential Revision: https://reviews.llvm.org/D75378
parent 0858eebd

llvm/include/llvm/MC/LaneBitmask.h

+3 −3
Original line number Diff line number Diff line
@@ -38,9 +38,9 @@ namespace llvm { 


  struct LaneBitmask {

    // When changing the underlying type, change the format string as well.

    using Type = unsigned;

    using Type = uint64_t;

    enum : unsigned { BitWidth = 8*sizeof(Type) };

    constexpr static const char *const FormatStr = "%08X";

    constexpr static const char *const FormatStr = "%016lX";



    constexpr LaneBitmask() = default;

    explicit constexpr LaneBitmask(Type V) : Mask(V) {}
@@ -76,7 +76,7 @@ namespace llvm { 
      return countPopulation(Mask);

    }

    unsigned getHighestLane() const {

      return Log2_32(Mask);

      return Log2_64(Mask);

    }



    static constexpr LaneBitmask getNone() { return LaneBitmask(0); }

llvm/lib/CodeGen/MIRParser/MIParser.cpp

+2 −2
Original line number Diff line number Diff line
@@ -750,10 +750,10 @@ bool MIParser::parseBasicBlockLiveins(MachineBasicBlock &MBB) { 
      if (Token.isNot(MIToken::IntegerLiteral) &&

          Token.isNot(MIToken::HexLiteral))

        return error("expected a lane mask");

      static_assert(sizeof(LaneBitmask::Type) == sizeof(unsigned),

      static_assert(sizeof(LaneBitmask::Type) == sizeof(uint64_t),

                    "Use correct get-function for lane mask");

      LaneBitmask::Type V;

      if (getUnsigned(V))

      if (getUint64(V))

        return error("invalid lane mask value");

      Mask = LaneBitmask(V);

      lex();

llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir

+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
# CHECK-NEXT: - basic block: %bb.0

# CHECK-NEXT: - instruction: 48B	dead undef %2.sub0:vreg_128 = COPY %0.sub0:vreg_128

# CHECK-NEXT: - operand 1:   %0.sub0:vreg_128

# CHECK-NEXT: - interval:    %0 [16r,48r:0)  0@16r L00000002 [16r,32r:0)  0@16r weight:0.000000e+00

# CHECK-NEXT: - interval:    %0 [16r,48r:0)  0@16r L0000000000000002 [16r,32r:0)  0@16r weight:0.000000e+00



# This used to assert with: !SR.empty() && "At least one value should be defined by this mask"

llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir

+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
# CHECK-LABEL: bb.0:

# CHECK: renamable $sgpr1 = COPY renamable $sgpr2

# CHECK-LABEL: bb.1:

# CHECK: liveins: $sgpr0_sgpr1:0x00000003

# CHECK: liveins: $sgpr0_sgpr1:0x0000000000000003

# CHECK: renamable $vgpr1_vgpr2 = COPY renamable $sgpr0_sgpr1



---

llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir

+3 −3
Original line number Diff line number Diff line
@@ -40,21 +40,21 @@ body: | 
# CHECK-SUB: Bad machine code: Live range continues after dead def flag

# CHECK_SUB-NEXT: function:    test_fail

# CHECK-SUB:      v. register: %0

# CHECK-SUB:      lanemask:    00000002

# CHECK-SUB:      lanemask:    0000000000000002

#

# CHECK-SUB-NOT: Bad machine code

#

# CHECK-SUB: Bad machine code: Live range continues after dead def flag

# CHECK-SUB-NEXT: function:    test_fail

# CHECK-SUB:      v. register: %1

# CHECK-SUB:      lanemask:    00000002

# CHECK-SUB:      lanemask:    0000000000000002

#

# CHECK-SUB-NOT: Bad machine code

#

# CHECK-SUB: Bad machine code: Live range continues after dead def flag

# CHECK-SUB-NEXT: function:    test_fail

# CHECK-SUB:      v. register: %1

# CHECK-SUB:      lanemask:    00000001

# CHECK-SUB:      lanemask:    0000000000000001

#

# CHECK-SUB: Bad machine code: Live range continues after dead def flag

# CHECK-SUB-NEXT: function:    test_fail