Commit 1b264a82 authored by David Green's avatar David Green
Browse files

[ARM] Reegenerate MVE tests. NFC 

The mve-phireg.ll test no longer really tests what it was added for,
but the original case was fairly complex. I've left the test in as a
general codegen test.
parent 188f9a34

llvm/test/CodeGen/Thumb2/mve-phireg.ll

+176 −4
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s



; verify-machineinstrs previously caught the incorrect use of QPR in the stack reloads.



define arm_aapcs_vfpcc void @k() {

; CHECK-LABEL: k:

; CHECK:    vstrw.32

; CHECK:    vldrw.u32

; CHECK:       @ %bb.0: @ %entry

; CHECK-NEXT:    .save {r4, r5, r6, lr}

; CHECK-NEXT:    push {r4, r5, r6, lr}

; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}

; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}

; CHECK-NEXT:    .pad #16

; CHECK-NEXT:    sub sp, #16

; CHECK-NEXT:    adr r5, .LCPI0_0

; CHECK-NEXT:    adr r4, .LCPI0_1

; CHECK-NEXT:    vldrw.u32 q5, [r5]

; CHECK-NEXT:    vldrw.u32 q6, [r4]

; CHECK-NEXT:    vmov.i32 q0, #0x1

; CHECK-NEXT:    vmov.i8 q1, #0x0

; CHECK-NEXT:    vmov.i8 q2, #0xff

; CHECK-NEXT:    vmov.i16 q3, #0x6

; CHECK-NEXT:    vmov.i16 q4, #0x3

; CHECK-NEXT:    movs r0, #0

; CHECK-NEXT:  .LBB0_1: @ %vector.body

; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1

; CHECK-NEXT:    vand q5, q5, q0

; CHECK-NEXT:    vand q6, q6, q0

; CHECK-NEXT:    vcmp.i32 eq, q5, zr

; CHECK-NEXT:    vpsel q5, q2, q1

; CHECK-NEXT:    vcmp.i32 eq, q6, zr

; CHECK-NEXT:    vpsel q7, q2, q1

; CHECK-NEXT:    vmov r1, s28

; CHECK-NEXT:    vmov.16 q6[0], r1

; CHECK-NEXT:    vmov r1, s29

; CHECK-NEXT:    vmov.16 q6[1], r1

; CHECK-NEXT:    vmov r1, s30

; CHECK-NEXT:    vmov.16 q6[2], r1

; CHECK-NEXT:    vmov r1, s31

; CHECK-NEXT:    vmov.16 q6[3], r1

; CHECK-NEXT:    vmov r1, s20

; CHECK-NEXT:    vmov.16 q6[4], r1

; CHECK-NEXT:    vmov r1, s21

; CHECK-NEXT:    vmov.16 q6[5], r1

; CHECK-NEXT:    vmov r1, s22

; CHECK-NEXT:    vmov.16 q6[6], r1

; CHECK-NEXT:    vmov r1, s23

; CHECK-NEXT:    vmov.16 q6[7], r1

; CHECK-NEXT:    vcmp.i16 ne, q6, zr

; CHECK-NEXT:    vmov.i32 q6, #0x0

; CHECK-NEXT:    vpsel q5, q4, q3

; CHECK-NEXT:    vstrh.16 q5, [r0]

; CHECK-NEXT:    vmov q5, q6

; CHECK-NEXT:    cbz r0, .LBB0_2

; CHECK-NEXT:    le .LBB0_1

; CHECK-NEXT:  .LBB0_2: @ %for.cond4.preheader

; CHECK-NEXT:    movs r6, #0

; CHECK-NEXT:    cbnz r6, .LBB0_5

; CHECK-NEXT:  .LBB0_3: @ %for.body10

; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1

; CHECK-NEXT:    cbnz r6, .LBB0_4

; CHECK-NEXT:    le .LBB0_3

; CHECK-NEXT:  .LBB0_4: @ %for.cond4.loopexit

; CHECK-NEXT:    bl l

; CHECK-NEXT:  .LBB0_5: @ %vector.body105.preheader

; CHECK-NEXT:    vldrw.u32 q0, [r5]

; CHECK-NEXT:    vldrw.u32 q1, [r4]

; CHECK-NEXT:    vmov.i32 q2, #0x8

; CHECK-NEXT:  .LBB0_6: @ %vector.body105

; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1

; CHECK-NEXT:    vadd.i32 q1, q1, q2

; CHECK-NEXT:    vadd.i32 q0, q0, q2

; CHECK-NEXT:    cbz r6, .LBB0_7

; CHECK-NEXT:    le .LBB0_6

; CHECK-NEXT:  .LBB0_7: @ %vector.body115.ph

; CHECK-NEXT:    vldrw.u32 q0, [r4]

; CHECK-NEXT:    vstrw.32 q0, [sp] @ 16-byte Spill

; CHECK-NEXT:    @APP

; CHECK-NEXT:    nop

; CHECK-NEXT:    @NO_APP

; CHECK-NEXT:    vldrw.u32 q1, [sp] @ 16-byte Reload

; CHECK-NEXT:    vmov.i32 q0, #0x4

; CHECK-NEXT:  .LBB0_8: @ %vector.body115

; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1

; CHECK-NEXT:    vadd.i32 q1, q1, q0

; CHECK-NEXT:    b .LBB0_8

; CHECK-NEXT:    .p2align 4

; CHECK-NEXT:  @ %bb.9:

; CHECK-NEXT:  .LCPI0_0:

; CHECK-NEXT:    .long 4 @ 0x4

; CHECK-NEXT:    .long 5 @ 0x5

; CHECK-NEXT:    .long 6 @ 0x6

; CHECK-NEXT:    .long 7 @ 0x7

; CHECK-NEXT:  .LCPI0_1:

; CHECK-NEXT:    .long 0 @ 0x0

; CHECK-NEXT:    .long 1 @ 0x1

; CHECK-NEXT:    .long 2 @ 0x2

; CHECK-NEXT:    .long 3 @ 0x3

entry:

  br label %vector.body
@@ -56,8 +146,90 @@ vector.body115: ; preds = %vector.body115, %ve 


define dso_local i32 @e() #0 {

; CHECK-LABEL: e:

; CHECK:    vstrw.32

; CHECK:    vldrw.u32

; CHECK:       @ %bb.0: @ %entry

; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}

; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}

; CHECK-NEXT:    .pad #4

; CHECK-NEXT:    sub sp, #4

; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}

; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}

; CHECK-NEXT:    .pad #440

; CHECK-NEXT:    sub sp, #440

; CHECK-NEXT:    vldr s20, .LCPI1_0

; CHECK-NEXT:    movw r9, :lower16:.L_MergedGlobals

; CHECK-NEXT:    vldr s23, .LCPI1_1

; CHECK-NEXT:    movt r9, :upper16:.L_MergedGlobals

; CHECK-NEXT:    mov.w r8, #4

; CHECK-NEXT:    mov r5, r9

; CHECK-NEXT:    strh.w r8, [sp, #438]

; CHECK-NEXT:    movs r6, #0

; CHECK-NEXT:    vstr s23, [sp, #48]

; CHECK-NEXT:    mov r7, r9

; CHECK-NEXT:    vstr s23, [sp, #40]

; CHECK-NEXT:    movw r4, :lower16:e

; CHECK-NEXT:    ldr r1, [r5, #4]!

; CHECK-NEXT:    movt r4, :upper16:e

; CHECK-NEXT:    str r6, [sp, #76]

; CHECK-NEXT:    vmov s5, r4

; CHECK-NEXT:    vmov.32 q7[0], r5

; CHECK-NEXT:    ldr r0, [r7, #8]!

; CHECK-NEXT:    vmov q0, q7

; CHECK-NEXT:    ldr r2, [sp, #48]

; CHECK-NEXT:    vmov.32 q0[1], r5

; CHECK-NEXT:    vmov s21, r5

; CHECK-NEXT:    vmov.32 q0[2], r2

; CHECK-NEXT:    ldr r2, [sp, #40]

; CHECK-NEXT:    vdup.32 q2, r5

; CHECK-NEXT:    vmov.32 q4[0], r7

; CHECK-NEXT:    vmov q6, q4

; CHECK-NEXT:    vstrw.32 q2, [sp] @ 16-byte Spill

; CHECK-NEXT:    vmov.32 q6[1], r2

; CHECK-NEXT:    vldrw.u32 q3, [sp] @ 16-byte Reload

; CHECK-NEXT:    vmov.f32 s22, s21

; CHECK-NEXT:    vmov.32 q6[2], r7

; CHECK-NEXT:    vmov.f32 s4, s20

; CHECK-NEXT:    vstrw.32 q2, [sp, #16] @ 16-byte Spill

; CHECK-NEXT:    vmov.f32 s6, s21

; CHECK-NEXT:    vmov.32 q3[0], r4

; CHECK-NEXT:    vmov.32 q2[1], r4

; CHECK-NEXT:    vmov.32 q6[3], r4

; CHECK-NEXT:    vmov.32 q0[3], r4

; CHECK-NEXT:    vmov.f32 s7, s23

; CHECK-NEXT:    str r1, [sp, #72]

; CHECK-NEXT:    vstrw.32 q6, [sp, #124]

; CHECK-NEXT:    str r1, [r0]

; CHECK-NEXT:    movs r1, #64

; CHECK-NEXT:    str r0, [r0]

; CHECK-NEXT:    vstrw.32 q5, [sp, #92]

; CHECK-NEXT:    vstrw.32 q1, [r0]

; CHECK-NEXT:    vstrw.32 q2, [r0]

; CHECK-NEXT:    vstrw.32 q3, [r0]

; CHECK-NEXT:    vstrw.32 q0, [r0]

; CHECK-NEXT:    bl __aeabi_memclr4

; CHECK-NEXT:    vstr s23, [sp, #44]

; CHECK-NEXT:    vmov.32 q7[1], r7

; CHECK-NEXT:    ldr r0, [sp, #44]

; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload

; CHECK-NEXT:    vmov.32 q4[1], r4

; CHECK-NEXT:    vmov.32 q7[2], r5

; CHECK-NEXT:    vmov.32 q4[2], r5

; CHECK-NEXT:    vmov.32 q0[0], r6

; CHECK-NEXT:    vmov.32 q4[3], r7

; CHECK-NEXT:    vmov.32 q7[3], r0

; CHECK-NEXT:    vstrw.32 q4, [r0]

; CHECK-NEXT:    str.w r6, [r9]

; CHECK-NEXT:    vstrw.32 q0, [r0]

; CHECK-NEXT:    vstrw.32 q7, [r0]

; CHECK-NEXT:    str.w r8, [sp, #356]

; CHECK-NEXT:  .LBB1_1: @ %for.cond

; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1

; CHECK-NEXT:    b .LBB1_1

; CHECK-NEXT:    .p2align 2

; CHECK-NEXT:  @ %bb.2:

; CHECK-NEXT:  .LCPI1_0:

; CHECK-NEXT:    .long 4 @ float 5.60519386E-45

; CHECK-NEXT:  .LCPI1_1:

; CHECK-NEXT:    .long 0 @ float 0

entry:

  %f = alloca i16, align 2

  %g = alloca [3 x [8 x [4 x i16*]]], align 4

llvm/test/CodeGen/Thumb2/mve-stacksplot.mir

+90 −92
Original line number Diff line number Diff line
@@ -12,52 +12,51 @@ body: | 
  bb.0:

    ; CHECK-LABEL: name: func0

    ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr

    ; CHECK-NEXT: {{  }}

    ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36

    ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 56

    ; CHECK-NEXT: $r0 = IMPLICIT_DEF

    ; CHECK-NEXT: $r1 = IMPLICIT_DEF

    ; CHECK-NEXT: $r2 = IMPLICIT_DEF

    ; CHECK-NEXT: $r3 = IMPLICIT_DEF

    ; CHECK-NEXT: $r4 = IMPLICIT_DEF

    ; CHECK-NEXT: $r5 = IMPLICIT_DEF

    ; CHECK-NEXT: $r6 = IMPLICIT_DEF

    ; CHECK-NEXT: $r7 = IMPLICIT_DEF

    ; CHECK-NEXT: $r8 = IMPLICIT_DEF

    ; CHECK-NEXT: $r9 = IMPLICIT_DEF

    ; CHECK-NEXT: $r10 = IMPLICIT_DEF

    ; CHECK-NEXT: $r11 = IMPLICIT_DEF

    ; CHECK-NEXT: $r12 = IMPLICIT_DEF

    ; CHECK-NEXT: $lr = IMPLICIT_DEF

    ; CHECK-NEXT: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1)

    ; CHECK-NEXT: $r0 = tMOVr killed $sp, 14, $noreg

    ; CHECK-NEXT: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12)

    ; CHECK-NEXT: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1)

    ; CHECK-NEXT: KILL $r0

    ; CHECK-NEXT: KILL $r1

    ; CHECK-NEXT: KILL $r2

    ; CHECK-NEXT: KILL $r3

    ; CHECK-NEXT: KILL $r4

    ; CHECK-NEXT: KILL $r5

    ; CHECK-NEXT: KILL $r6

    ; CHECK-NEXT: KILL $r7

    ; CHECK-NEXT: KILL $r8

    ; CHECK-NEXT: KILL $r9

    ; CHECK-NEXT: KILL $r10

    ; CHECK-NEXT: KILL $r11

    ; CHECK-NEXT: KILL $r12

    ; CHECK-NEXT: KILL $lr

    ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr

    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36

    ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36

    ; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg

    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56

    ; CHECK: $r0 = IMPLICIT_DEF

    ; CHECK: $r1 = IMPLICIT_DEF

    ; CHECK: $r2 = IMPLICIT_DEF

    ; CHECK: $r3 = IMPLICIT_DEF

    ; CHECK: $r4 = IMPLICIT_DEF

    ; CHECK: $r5 = IMPLICIT_DEF

    ; CHECK: $r6 = IMPLICIT_DEF

    ; CHECK: $r7 = IMPLICIT_DEF

    ; CHECK: $r8 = IMPLICIT_DEF

    ; CHECK: $r9 = IMPLICIT_DEF

    ; CHECK: $r10 = IMPLICIT_DEF

    ; CHECK: $r11 = IMPLICIT_DEF

    ; CHECK: $r12 = IMPLICIT_DEF

    ; CHECK: $lr = IMPLICIT_DEF

    ; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1)

    ; CHECK: $r0 = tMOVr killed $sp, 14, $noreg

    ; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12)

    ; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1)

    ; CHECK: KILL $r0

    ; CHECK: KILL $r1

    ; CHECK: KILL $r2

    ; CHECK: KILL $r3

    ; CHECK: KILL $r4

    ; CHECK: KILL $r5

    ; CHECK: KILL $r6

    ; CHECK: KILL $r7

    ; CHECK: KILL $r8

    ; CHECK: KILL $r9

    ; CHECK: KILL $r10

    ; CHECK: KILL $r11

    ; CHECK: KILL $r12

    ; CHECK: KILL $lr

    $r0 = IMPLICIT_DEF

    $r1 = IMPLICIT_DEF

    $r2 = IMPLICIT_DEF
@@ -106,52 +105,51 @@ body: | 
  bb.0:

    ; CHECK-LABEL: name: func1

    ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr

    ; CHECK-NEXT: {{  }}

    ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36

    ; CHECK-NEXT: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14, $noreg

    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 1256

    ; CHECK-NEXT: $r0 = IMPLICIT_DEF

    ; CHECK-NEXT: $r1 = IMPLICIT_DEF

    ; CHECK-NEXT: $r2 = IMPLICIT_DEF

    ; CHECK-NEXT: $r3 = IMPLICIT_DEF

    ; CHECK-NEXT: $r4 = IMPLICIT_DEF

    ; CHECK-NEXT: $r5 = IMPLICIT_DEF

    ; CHECK-NEXT: $r6 = IMPLICIT_DEF

    ; CHECK-NEXT: $r7 = IMPLICIT_DEF

    ; CHECK-NEXT: $r8 = IMPLICIT_DEF

    ; CHECK-NEXT: $r9 = IMPLICIT_DEF

    ; CHECK-NEXT: $r10 = IMPLICIT_DEF

    ; CHECK-NEXT: $r11 = IMPLICIT_DEF

    ; CHECK-NEXT: $r12 = IMPLICIT_DEF

    ; CHECK-NEXT: $lr = IMPLICIT_DEF

    ; CHECK-NEXT: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2)

    ; CHECK-NEXT: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg

    ; CHECK-NEXT: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0)

    ; CHECK-NEXT: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2)

    ; CHECK-NEXT: KILL $r0

    ; CHECK-NEXT: KILL $r1

    ; CHECK-NEXT: KILL $r2

    ; CHECK-NEXT: KILL $r3

    ; CHECK-NEXT: KILL $r4

    ; CHECK-NEXT: KILL $r5

    ; CHECK-NEXT: KILL $r6

    ; CHECK-NEXT: KILL $r7

    ; CHECK-NEXT: KILL $r8

    ; CHECK-NEXT: KILL $r9

    ; CHECK-NEXT: KILL $r10

    ; CHECK-NEXT: KILL $r11

    ; CHECK-NEXT: KILL $r12

    ; CHECK-NEXT: KILL $lr

    ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr

    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36

    ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36

    ; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14, $noreg

    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256

    ; CHECK: $r0 = IMPLICIT_DEF

    ; CHECK: $r1 = IMPLICIT_DEF

    ; CHECK: $r2 = IMPLICIT_DEF

    ; CHECK: $r3 = IMPLICIT_DEF

    ; CHECK: $r4 = IMPLICIT_DEF

    ; CHECK: $r5 = IMPLICIT_DEF

    ; CHECK: $r6 = IMPLICIT_DEF

    ; CHECK: $r7 = IMPLICIT_DEF

    ; CHECK: $r8 = IMPLICIT_DEF

    ; CHECK: $r9 = IMPLICIT_DEF

    ; CHECK: $r10 = IMPLICIT_DEF

    ; CHECK: $r11 = IMPLICIT_DEF

    ; CHECK: $r12 = IMPLICIT_DEF

    ; CHECK: $lr = IMPLICIT_DEF

    ; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2)

    ; CHECK: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg

    ; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0)

    ; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2)

    ; CHECK: KILL $r0

    ; CHECK: KILL $r1

    ; CHECK: KILL $r2

    ; CHECK: KILL $r3

    ; CHECK: KILL $r4

    ; CHECK: KILL $r5

    ; CHECK: KILL $r6

    ; CHECK: KILL $r7

    ; CHECK: KILL $r8

    ; CHECK: KILL $r9

    ; CHECK: KILL $r10

    ; CHECK: KILL $r11

    ; CHECK: KILL $r12

    ; CHECK: KILL $lr

    $r0 = IMPLICIT_DEF

    $r1 = IMPLICIT_DEF

    $r2 = IMPLICIT_DEF

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir

+15 −13
Original line number Diff line number Diff line
@@ -62,7 +62,11 @@ body: | 
  bb.0:

  liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12







    ; CHECK-LABEL: name: vpt_2_blocks_1_pred

    ; CHECK: successors: %bb.0(0x80000000)

    ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12

    ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg

    ; CHECK: BUNDLE implicit-def $vpr, implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $q1, implicit $q5, implicit killed $r4 {

    ; CHECK:   MVE_VPTv4u32 8, renamable $q1, renamable $q5, 2, implicit-def $vpr
@@ -75,8 +79,6 @@ body: | 
    ; CHECK: }

    ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr

    ; CHECK: t2B %bb.0, 14, $noreg





  renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg

  renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg

  renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir

+1 −1
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ body: | 
  bb.0.entry:

    liveins: $q0, $q1, $q2, $r0





    ; CHECK-LABEL: name: vpt_2_blocks_non_consecutive_ins

    ; CHECK: liveins: $q0, $q1, $q2, $r0

    ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
@@ -80,7 +81,6 @@ body: | 
    ; CHECK:   renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0

    ; CHECK: }

    ; CHECK: tBX_RET 14, $noreg, implicit $q0



    $vpr = VMSR_P0 killed $r0, 14, $noreg

    $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3

    renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3

llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir

+25 −12
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s



--- |
@@ -94,6 +95,18 @@ body: | 
  bb.0.entry:

    liveins: $q0, $r0, $r1, $r2, $lr





    ; CHECK-LABEL: name: foo

    ; CHECK: liveins: $q0, $r0, $r1, $r2, $lr

    ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr

    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8

    ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4

    ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8

    ; CHECK: $r7 = frame-setup tMOVr killed $sp, 14, $noreg

    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7

    ; CHECK: renamable $r12 = t2LDRi12 $r7, 16, 14, $noreg :: (load 4 from %fixed-stack.2)

    ; CHECK: renamable $lr = t2LDRi12 $r7, 12, 14, $noreg :: (load 4 from %fixed-stack.1)

    ; CHECK: renamable $r3 = t2LDRi12 $r7, 8, 14, $noreg :: (load 4 from %fixed-stack.0)

    ; CHECK: BUNDLE implicit-def $vpr, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $q0, implicit $zr, implicit killed $r0, implicit killed $r3, implicit killed $r1, implicit killed $lr {

    ; CHECK:   MVE_VPTv4f32r 1, renamable $q0, $zr, 10, implicit-def $vpr

    ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, internal renamable $vpr :: (load 16 from %ir.src, align 4)
@@ -106,7 +119,7 @@ body: | 
    ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr :: (load 16 from %ir.src3, align 4)

    ; CHECK:   MVE_VSTRWU32 internal renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr :: (store 16 into %ir.dest3, align 4)

    ; CHECK: }



    ; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $q0

    $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr

    frame-setup CFI_INSTRUCTION def_cfa_offset 8

    frame-setup CFI_INSTRUCTION offset $lr, -4