Unverified Commit 17baba9f authored by hassnaaHamdi's avatar hassnaaHamdi Committed by GitHub
Browse files

[llvm][AArch64][Assembly] Implement support to read/write FPMR (#69618) 

Also add  Read only registers:
   ID_AA64FPFR0_EL1
   ID_AA64ISAR3_EL1

This is based on this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09



Co-authored-by: default avatarCaroline Concatto <caroline.concatto@arm.com>
parent 6d53fdea

llvm/include/llvm/TargetParser/AArch64TargetParser.h

+3 −1
Original line number Diff line number Diff line
@@ -159,7 +159,8 @@ enum ArchExtKind : unsigned { 
  AEK_RASv2 =         55, // FEAT_RASv2

  AEK_ITE =           56, // FEAT_ITE

  AEK_GCS =           57, // FEAT_GCS

  AEK_NUM_EXTENSIONS =  AEK_GCS + 1

  AEK_FPMR =          58, // FEAT_FPMR

  AEK_NUM_EXTENSIONS

};

using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;

// clang-format on
@@ -267,6 +268,7 @@ inline constexpr ExtensionInfo Extensions[] = { 
    {"tme", AArch64::AEK_TME, "+tme", "-tme", FEAT_INIT, "", 0},

    {"wfxt", AArch64::AEK_NONE, {}, {}, FEAT_WFXT, "+wfxt", 550},

    {"gcs", AArch64::AEK_GCS, "+gcs", "-gcs", FEAT_INIT, "", 0},

    {"fpmr", AArch64::AEK_FPMR, "+fpmr", "-fpmr", FEAT_INIT, "", 0},

    // Special cases

    {"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},

};

llvm/lib/Target/AArch64/AArch64.td

+3 −0
Original line number Diff line number Diff line
@@ -127,6 +127,9 @@ def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 
def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",

  "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>;



def FeatureFPMR : SubtargetFeature<"fpmr", "HasFPMR", "true",

  "Enable FPMR Register (FEAT_FPMR)">;



// This flag is currently still labeled as Experimental, but when fully

// implemented this should tell the compiler to use the zeroing pseudos to

// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive

llvm/lib/Target/AArch64/AArch64InstrInfo.td

+2 −0
Original line number Diff line number Diff line
@@ -160,6 +160,8 @@ def HasSME2 : Predicate<"Subtarget->hasSME2()">, 
                                 AssemblerPredicateWithAll<(all_of FeatureSME2), "sme2">;

def HasSME2p1        : Predicate<"Subtarget->hasSME2p1()">,

                                 AssemblerPredicateWithAll<(all_of FeatureSME2p1), "sme2p1">;

def HasFPMR          : Predicate<"Subtarget->hasFPMR()">,

                                 AssemblerPredicateWithAll<(all_of FeatureFPMR), "fpmr">;



// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,

// they should be enabled if either has been specified.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

+10 −0
Original line number Diff line number Diff line
@@ -743,6 +743,7 @@ def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>; 
def : ROSysReg<"ID_AA64ISAR0_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b000>;

def : ROSysReg<"ID_AA64ISAR1_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b001>;

def : ROSysReg<"ID_AA64ISAR2_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b010>;

def : ROSysReg<"ID_AA64ISAR3_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b011>;

def : ROSysReg<"ID_AA64MMFR0_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b000>;

def : ROSysReg<"ID_AA64MMFR1_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b001>;

def : ROSysReg<"ID_AA64MMFR2_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b010>;
@@ -1927,3 +1928,12 @@ def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>; 
// v9.4a Exception-based event profiling (FEAT_EBEP)

//                                  Op0   Op1    CRn     CRm     Op2

def : RWSysReg<"PM",                0b11, 0b000, 0b0100, 0b0011, 0b001>;



// 2023 ISA Extension

// AArch64 Floating-point Mode Register controls behaviors of the FP8

// instructions (FEAT_FPMR)

let Requires = [{ {AArch64::FeatureFPMR} }] in {

//                                 Op0   Op1    CRn     CRm     Op2

def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>;

def : RWSysReg<"FPMR",             0b11, 0b011, 0b0100, 0b0100, 0b010>;

}

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

+1 −0
Original line number Diff line number Diff line
@@ -3638,6 +3638,7 @@ static const struct Extension { 
    {"sb", {AArch64::FeatureSB}},

    {"ssbs", {AArch64::FeatureSSBS}},

    {"tme", {AArch64::FeatureTME}},

    {"fpmr", {AArch64::FeatureFPMR}},

};



static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {