Unverified Commit 17970df6 authored by Paul Walker's avatar Paul Walker Committed by GitHub
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[LLVM][SVE] Move ADDVL isel patterns under UseScalarIncVL feature flag. (#71173)

Also removes a duplicate pattern.
parent 05a47706
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+8 −11
Original line number Diff line number Diff line
@@ -2423,14 +2423,6 @@ let Predicates = [HasSVEorSME] in {
  }

  let AddedComplexity = 5 in {
    def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
              (ADDVL_XXI GPR64:$op, $imm)>;

    def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_rdvl_imm i32:$imm))))),
              (i32 (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
                                             GPR32:$op, sub_32), $imm),
                                   sub_32))>;

    def : Pat<(nxv8i16 (add ZPR:$op, (nxv8i16 (splat_vector (i32 (trunc (vscale (sve_cnth_imm i32:$imm)))))))),
              (INCH_ZPiI ZPR:$op, 31, $imm)>;
    def : Pat<(nxv4i32 (add ZPR:$op, (nxv4i32 (splat_vector (i32 (trunc (vscale (sve_cntw_imm i32:$imm)))))))),
@@ -2447,6 +2439,14 @@ let Predicates = [HasSVEorSME] in {
  }

  let Predicates = [HasSVEorSME, UseScalarIncVL], AddedComplexity = 5 in {
    def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
              (ADDVL_XXI GPR64:$op, $imm)>;

    def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_rdvl_imm i32:$imm))))),
              (i32 (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
                                             GPR32:$op, sub_32), $imm),
                                   sub_32))>;

    def : Pat<(add GPR64:$op, (vscale (sve_cnth_imm i32:$imm))),
              (INCH_XPiI GPR64:$op, 31, $imm)>;
    def : Pat<(add GPR64:$op, (vscale (sve_cntw_imm i32:$imm))),
@@ -2488,9 +2488,6 @@ let Predicates = [HasSVEorSME] in {
                                    sub_32))>;
  }

  def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
            (ADDVL_XXI GPR64:$op, $imm)>;

  // FIXME: BigEndian requires an additional REV instruction to satisfy the
  // constraint that none of the bits change when stored to memory as one
  // type, and reloaded as another type.
+4 −3
Original line number Diff line number Diff line
@@ -195,13 +195,14 @@ define %"class.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) {
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    neg x10, x9
; CHECK-NEXT:    mov w11, #1000 // =0x3e8
; CHECK-NEXT:    rdvl x13, #2
; CHECK-NEXT:    mov x8, xzr
; CHECK-NEXT:    and x10, x10, x11
; CHECK-NEXT:    rdvl x11, #4
; CHECK-NEXT:    zip2 z0.d, z1.d, z1.d
; CHECK-NEXT:    zip1 z1.d, z1.d, z1.d
; CHECK-NEXT:    addvl x12, x1, #2
; CHECK-NEXT:    addvl x13, x0, #2
; CHECK-NEXT:    rdvl x11, #4
; CHECK-NEXT:    add x12, x1, x13
; CHECK-NEXT:    add x13, x0, x13
; CHECK-NEXT:    mov z2.d, z1.d
; CHECK-NEXT:    mov z3.d, z0.d
; CHECK-NEXT:  .LBB2_1: // %vector.body
+11 −10
Original line number Diff line number Diff line
@@ -351,9 +351,9 @@ define <vscale x 16 x float> @splice_nxv16f32_16(<vscale x 16 x float> %a, <vsca
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-8
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    mov x8, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    rdvl x8, #1
; CHECK-NEXT:    mov w9, #16 // =0x10
; CHECK-NEXT:    addvl x8, x8, #1
; CHECK-NEXT:    sub x8, x8, #1
; CHECK-NEXT:    cmp x8, #16
; CHECK-NEXT:    csel x8, x8, x9, lo
; CHECK-NEXT:    mov x9, sp
@@ -457,7 +457,7 @@ define <vscale x 16 x i8> @splice_nxv16i8_neg17(<vscale x 16 x i8> %a, <vscale x
; CHECK-NEXT:    mov w9, #17 // =0x11
; CHECK-NEXT:    mov x10, sp
; CHECK-NEXT:    cmp x8, #17
; CHECK-NEXT:    addvl x10, x10, #1
; CHECK-NEXT:    add x10, x10, x8
; CHECK-NEXT:    csel x8, x8, x9, lo
; CHECK-NEXT:    sub x8, x10, x8
; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
@@ -502,7 +502,7 @@ define <vscale x 8 x i16> @splice_nxv8i16_neg9(<vscale x 8 x i16> %a, <vscale x
; CHECK-NEXT:    mov w9, #18 // =0x12
; CHECK-NEXT:    mov x10, sp
; CHECK-NEXT:    cmp x8, #18
; CHECK-NEXT:    addvl x10, x10, #1
; CHECK-NEXT:    add x10, x10, x8
; CHECK-NEXT:    csel x8, x8, x9, lo
; CHECK-NEXT:    sub x8, x10, x8
; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
@@ -613,7 +613,7 @@ define <vscale x 8 x half> @splice_nxv8f16_neg9(<vscale x 8 x half> %a, <vscale
; CHECK-NEXT:    mov w9, #18 // =0x12
; CHECK-NEXT:    mov x10, sp
; CHECK-NEXT:    cmp x8, #18
; CHECK-NEXT:    addvl x10, x10, #1
; CHECK-NEXT:    add x10, x10, x8
; CHECK-NEXT:    csel x8, x8, x9, lo
; CHECK-NEXT:    sub x8, x10, x8
; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
@@ -779,9 +779,10 @@ define <vscale x 8 x i32> @splice_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-4
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    mov x8, sp
; CHECK-NEXT:    rdvl x8, #2
; CHECK-NEXT:    mov x9, sp
; CHECK-NEXT:    add x8, x9, x8
; CHECK-NEXT:    mov x9, #-8 // =0xfffffffffffffff8
; CHECK-NEXT:    addvl x8, x8, #2
; CHECK-NEXT:    sub x10, x8, #32
; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
@@ -807,9 +808,9 @@ define <vscale x 16 x float> @splice_nxv16f32_neg17(<vscale x 16 x float> %a, <v
; CHECK-NEXT:    mov w9, #68 // =0x44
; CHECK-NEXT:    mov x10, sp
; CHECK-NEXT:    cmp x8, #68
; CHECK-NEXT:    csel x8, x8, x9, lo
; CHECK-NEXT:    addvl x9, x10, #4
; CHECK-NEXT:    sub x8, x9, x8
; CHECK-NEXT:    csel x9, x8, x9, lo
; CHECK-NEXT:    add x8, x10, x8
; CHECK-NEXT:    sub x8, x8, x9
; CHECK-NEXT:    st1w { z3.s }, p0, [sp, #3, mul vl]
; CHECK-NEXT:    st1w { z2.s }, p0, [sp, #2, mul vl]
; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
+2 −2
Original line number Diff line number Diff line
@@ -215,9 +215,9 @@ define <16 x i8> @extract_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec) nounwind
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-1
; CHECK-NEXT:    ptrue p0.b
; CHECK-NEXT:    mov x8, #-16 // =0xfffffffffffffff0
; CHECK-NEXT:    rdvl x8, #1
; CHECK-NEXT:    mov w9, #16 // =0x10
; CHECK-NEXT:    addvl x8, x8, #1
; CHECK-NEXT:    sub x8, x8, #16
; CHECK-NEXT:    cmp x8, #16
; CHECK-NEXT:    csel x8, x8, x9, lo
; CHECK-NEXT:    mov x9, sp
+4 −2
Original line number Diff line number Diff line
@@ -4,7 +4,8 @@
define <vscale x 2 x i64>* @scalar_of_scalable_1(<vscale x 2 x i64>* %base) {
; CHECK-LABEL: scalar_of_scalable_1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    addvl x0, x0, #4
; CHECK-NEXT:    rdvl x8, #4
; CHECK-NEXT:    add x0, x0, x8
; CHECK-NEXT:    ret
  %d = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 4
  ret <vscale x 2 x i64>* %d
@@ -202,7 +203,8 @@ define <vscale x 2 x i64*> @scalable_of_fixed_5_i64(i64* %base, <vscale x 2 x i3
define <vscale x 2 x <vscale x 2 x i64>*> @scalable_of_scalable_1(<vscale x 2 x i64>* %base) {
; CHECK-LABEL: scalable_of_scalable_1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    addvl x8, x0, #1
; CHECK-NEXT:    rdvl x8, #1
; CHECK-NEXT:    add x8, x0, x8
; CHECK-NEXT:    mov z0.d, x8
; CHECK-NEXT:    ret
  %idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
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