Commit 13fe6733 authored by Craig Topper's avatar Craig Topper
Browse files

[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. 

Rather than having a separate pass to add the hint instructions,
emit them directly into the streamer during asm printing.

Reviewed By: BeMg, kito-cheng

Differential Revision: https://reviews.llvm.org/D149511
parent 4ca19327

llvm/lib/Target/RISCV/CMakeLists.txt

+0 −1
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ add_llvm_target(RISCVCodeGen 
  RISCVExpandPseudoInsts.cpp

  RISCVFrameLowering.cpp

  RISCVGatherScatterLowering.cpp

  RISCVInsertNTLHInsts.cpp

  RISCVInsertVSETVLI.cpp

  RISCVInstrInfo.cpp

  RISCVISelDAGToDAG.cpp

llvm/lib/Target/RISCV/RISCV.h

+0 −3
Original line number Diff line number Diff line
@@ -62,9 +62,6 @@ void initializeRISCVPreRAExpandPseudoPass(PassRegistry &); 
FunctionPass *createRISCVExpandAtomicPseudoPass();

void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);



FunctionPass *createRISCVInsertNTLHInstsPass();

void initializeRISCVInsertNTLHInstsPass(PassRegistry &);



FunctionPass *createRISCVInsertVSETVLIPass();

void initializeRISCVInsertVSETVLIPass(PassRegistry &);

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

+36 −0
Original line number Diff line number Diff line
@@ -85,6 +85,8 @@ public: 


private:

  void emitAttributes();



  void emitNTLHint(const MachineInstr *MI);

};

}
@@ -100,10 +102,44 @@ void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { 
// instructions) auto-generated.

#include "RISCVGenMCPseudoLowering.inc"



// If the target supports Zihintnthl and the instruction has a nontemporal

// MachineMemOperand, emit an NTLH hint instruction before it.

void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {

  if (!STI->hasStdExtZihintntl())

    return;



  if (MI->memoperands_empty())

    return;



  MachineMemOperand *MMO = *(MI->memoperands_begin());

  if (!MMO->isNonTemporal())

    return;



  unsigned NontemporalMode = 0;

  if (MMO->getFlags() & MONontemporalBit0)

    NontemporalMode += 0b1;

  if (MMO->getFlags() & MONontemporalBit1)

    NontemporalMode += 0b10;



  MCInst Hint;

  if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs())

    Hint.setOpcode(RISCV::C_ADD_HINT);

  else

    Hint.setOpcode(RISCV::ADD);



  Hint.addOperand(MCOperand::createReg(RISCV::X0));

  Hint.addOperand(MCOperand::createReg(RISCV::X0));

  Hint.addOperand(MCOperand::createReg(RISCV::X2 + NontemporalMode));



  EmitToStreamer(*OutStreamer, Hint);

}



void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {

  RISCV_MC::verifyInstructionPredicates(MI->getOpcode(),

                                        getSubtargetInfo().getFeatureBits());



  emitNTLHint(MI);



  // Do any auto-generated pseudo lowerings.

  if (emitPseudoExpansionLowering(*OutStreamer, MI))

    return;

llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp

deleted100644 → 0
+0 −108
Original line number Diff line number Diff line 
//===-- RISCVInsertNTLHInsts.cpp - Insert NTLH extension instrution -------===//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

//

// This file implements a function pass that inserts non-temporal hint

// instructions where needed.

//

// It checks the MachineMemOperand of all MachineInstr.

// If the instruction has a MachineMemOperand and isNontemporal is true,

// then ntlh instruction is inserted before it.

//

//===----------------------------------------------------------------------===//



#include "RISCV.h"

#include "RISCVInstrInfo.h"

#include "RISCVTargetMachine.h"



#include "llvm/CodeGen/MachineFunctionPass.h"

#include "llvm/CodeGen/MachineInstrBuilder.h"



using namespace llvm;



#define RISCV_INSERT_NTLH_INSTS_NAME "RISC-V insert NTLH instruction pass"



namespace {



class RISCVInsertNTLHInsts : public MachineFunctionPass {

public:

  const RISCVInstrInfo *TII;

  static char ID;



  RISCVInsertNTLHInsts() : MachineFunctionPass(ID) {

    initializeRISCVInsertNTLHInstsPass(*PassRegistry::getPassRegistry());

  }



  bool runOnMachineFunction(MachineFunction &MF) override;



  void getAnalysisUsage(AnalysisUsage &AU) const override {

    AU.setPreservesCFG();

    MachineFunctionPass::getAnalysisUsage(AU);

  }



  StringRef getPassName() const override {

    return RISCV_INSERT_NTLH_INSTS_NAME;

  }

};



} // end of anonymous namespace



char RISCVInsertNTLHInsts::ID = 0;



bool RISCVInsertNTLHInsts::runOnMachineFunction(MachineFunction &MF) {

  const auto &ST = MF.getSubtarget<RISCVSubtarget>();

  TII = ST.getInstrInfo();



  if (!ST.hasStdExtZihintntl())

    return false;



  bool Changed = false;

  for (auto &MBB : MF) {

    for (auto &MBBI : MBB) {

      if (MBBI.memoperands_empty())

        continue;

      MachineMemOperand *MMO = *(MBBI.memoperands_begin());

      if (MMO->isNonTemporal()) {

        uint64_t NontemporalMode = 0;

        if (MMO->getFlags() & MONontemporalBit0)

          NontemporalMode += 0b1;

        if (MMO->getFlags() & MONontemporalBit1)

          NontemporalMode += 0b10;



        static const uint16_t NTLOpc[] = {

            RISCV::PseudoNTLP1, RISCV::PseudoNTLPALL, RISCV::PseudoNTLS1,

            RISCV::PseudoNTLALL};

        static const uint16_t CNTLOpc[] = {

            RISCV::PseudoCNTLP1, RISCV::PseudoCNTLPALL, RISCV::PseudoCNTLS1,

            RISCV::PseudoCNTLALL};



        unsigned CurrNTLOpc;

        DebugLoc DL = MBBI.getDebugLoc();

        if (ST.hasStdExtCOrZca() && ST.enableRVCHintInstrs())

          CurrNTLOpc = CNTLOpc[NontemporalMode];

        else

          CurrNTLOpc = NTLOpc[NontemporalMode];



        BuildMI(MBB, MBBI, DL, TII->get(CurrNTLOpc));

        Changed = true;

      }

    }

  }



  return Changed;

}



INITIALIZE_PASS(RISCVInsertNTLHInsts, "riscv-insert-ntlh-insts",

                RISCV_INSERT_NTLH_INSTS_NAME, false, false)



namespace llvm {



FunctionPass *createRISCVInsertNTLHInstsPass() {

  return new RISCVInsertNTLHInsts();

}



} // end of namespace llvm

llvm/lib/Target/RISCV/RISCVInstrInfo.td

+0 −1
Original line number Diff line number Diff line
@@ -1911,7 +1911,6 @@ include "RISCVInstrInfoZfa.td" 
include "RISCVInstrInfoZfh.td"

include "RISCVInstrInfoZicbo.td"

include "RISCVInstrInfoZicond.td"

include "RISCVInstrInfoZihintntl.td"



//===----------------------------------------------------------------------===//

// Vendor extensions