Commit 13b25164 authored by Bill Wendling's avatar Bill Wendling
Browse files

Merging r182113: 


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r182113 | tstellar | 2013-05-17 08:23:21 -0700 (Fri, 17 May 2013) | 9 lines

R600: Fix encoding for R600 family GPUs

Reviewed-by: default avatarVincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320

NOTE: This is a candidate for the 3.3 branch.
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llvm-svn: 182174
parent 22019e87

llvm/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp

+7 −0
Original line number Diff line number Diff line
@@ -176,6 +176,13 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, 
    Emit((u_int32_t) 0, OS);

  } else {

    uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);

    if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&

       ((Desc.TSFlags & R600_InstFlag::OP1) ||

         Desc.TSFlags & R600_InstFlag::OP2)) {

      uint64_t ISAOpCode = Inst & (0x3FFULL << 39);

      Inst &= ~(0x3FFULL << 39);

      Inst |= ISAOpCode << 1;

    }

    Emit(Inst, OS);

  }

}

llvm/test/CodeGen/R600/r600-encoding.ll

0 → 100644
+24 −0
Original line number Diff line number Diff line 
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s

; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600-CHECK %s



; The earliest R600 GPUs have a slightly different encoding than the rest of

; the VLIW4/5 GPUs.



; EG-CHECK: @test

; EG-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]



; R600-CHECK: @test

; R600-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]



define void @test() {

entry:

  %0 = call float @llvm.R600.load.input(i32 0)

  %1 = call float @llvm.R600.load.input(i32 1)

  %2 = fmul float %0, %1

  call void @llvm.AMDGPU.store.output(float %2, i32 0)

  ret void

}



declare float @llvm.R600.load.input(i32) readnone



declare void @llvm.AMDGPU.store.output(float, i32)