Commit 12fa608a authored by Tianqing Wang's avatar Tianqing Wang
Browse files

[X86] Add CRC32 feature. 

d8faf038 implemented general-regs-only for X86 by disabling all features
with vector instructions. But the CRC32 instruction in SSE4.2 ISA, which uses
only GPRs, also becomes unavailable. This patch adds a CRC32 feature for this
instruction and allows it to be used with general-regs-only.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D105462
parent cc9260a0

clang/docs/ClangCommandLineReference.rst

+2 −0
Original line number Diff line number Diff line
@@ -3590,6 +3590,8 @@ X86 


.. option:: -mclzero, -mno-clzero



.. option:: -mcrc32, -mno-crc32



.. option:: -mcx16, -mno-cx16



.. option:: -menqcmd, -mno-enqcmd

clang/include/clang/Basic/BuiltinsX86.def

+3 −3
Original line number Diff line number Diff line
@@ -421,9 +421,9 @@ TARGET_BUILTIN(__builtin_ia32_pcmpestrio128, "iV16ciV16ciIc","ncV:128:", "sse4.2 
TARGET_BUILTIN(__builtin_ia32_pcmpestris128, "iV16ciV16ciIc","ncV:128:", "sse4.2")

TARGET_BUILTIN(__builtin_ia32_pcmpestriz128, "iV16ciV16ciIc","ncV:128:", "sse4.2")



TARGET_BUILTIN(__builtin_ia32_crc32qi, "UiUiUc", "nc", "sse4.2")

TARGET_BUILTIN(__builtin_ia32_crc32hi, "UiUiUs", "nc", "sse4.2")

TARGET_BUILTIN(__builtin_ia32_crc32si, "UiUiUi", "nc", "sse4.2")

TARGET_BUILTIN(__builtin_ia32_crc32qi, "UiUiUc", "nc", "crc32")

TARGET_BUILTIN(__builtin_ia32_crc32hi, "UiUiUs", "nc", "crc32")

TARGET_BUILTIN(__builtin_ia32_crc32si, "UiUiUi", "nc", "crc32")



// SSE4a

TARGET_BUILTIN(__builtin_ia32_extrqi, "V2OiV2OiIcIc", "ncV:128:", "sse4a")

clang/include/clang/Basic/BuiltinsX86_64.def

+1 −1
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ TARGET_BUILTIN(__builtin_ia32_cvttsd2si64, "OiV2d", "ncV:128:", "sse2") 
TARGET_BUILTIN(__builtin_ia32_movnti64, "vOi*Oi", "n", "sse2")

TARGET_BUILTIN(__builtin_ia32_vec_ext_v2di, "OiV2OiIi", "ncV:128:", "sse2")

TARGET_BUILTIN(__builtin_ia32_vec_set_v2di, "V2OiV2OiOiIi", "ncV:128:", "sse4.1")

TARGET_BUILTIN(__builtin_ia32_crc32di, "UOiUOiUOi", "nc", "sse4.2")

TARGET_BUILTIN(__builtin_ia32_crc32di, "UOiUOiUOi", "nc", "crc32")

TARGET_BUILTIN(__builtin_ia32_vec_ext_v4di, "OiV4OiIi", "ncV:256:", "avx")

TARGET_BUILTIN(__builtin_ia32_vec_set_v4di, "V4OiV4OiOiIi", "ncV:256:", "avx")

TARGET_BUILTIN(__builtin_ia32_rdfsbase32, "Ui", "n", "fsgsbase")

clang/include/clang/Driver/Options.td

+2 −0
Original line number Diff line number Diff line
@@ -4206,6 +4206,8 @@ def mwbnoinvd : Flag<["-"], "mwbnoinvd">, Group<m_x86_Features_Group>; 
def mno_wbnoinvd : Flag<["-"], "mno-wbnoinvd">, Group<m_x86_Features_Group>;

def mclzero : Flag<["-"], "mclzero">, Group<m_x86_Features_Group>;

def mno_clzero : Flag<["-"], "mno-clzero">, Group<m_x86_Features_Group>;

def mcrc32 : Flag<["-"], "mcrc32">, Group<m_x86_Features_Group>;

def mno_crc32 : Flag<["-"], "mno-crc32">, Group<m_x86_Features_Group>;

def mcx16 : Flag<["-"], "mcx16">, Group<m_x86_Features_Group>;

def mno_cx16 : Flag<["-"], "mno-cx16">, Group<m_x86_Features_Group>;

def menqcmd : Flag<["-"], "menqcmd">, Group<m_x86_Features_Group>;

clang/lib/Basic/Targets/X86.cpp

+12 −0
Original line number Diff line number Diff line
@@ -155,6 +155,12 @@ bool X86TargetInfo::initFeatureMap( 
      llvm::find(UpdatedFeaturesVec, "-xsave") == UpdatedFeaturesVec.end())

    Features["xsave"] = true;



  // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.

  I = Features.find("sse4.2");

  if (I != Features.end() && I->getValue() &&

      llvm::find(UpdatedFeaturesVec, "-crc32") == UpdatedFeaturesVec.end())

    Features["crc32"] = true;



  return true;

}
@@ -330,6 +336,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 
      HasTSXLDTRK = true;

    } else if (Feature == "+uintr") {

      HasUINTR = true;

    } else if (Feature == "+crc32") {

      HasCRC32 = true;

    }



    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
@@ -758,6 +766,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 
    Builder.defineMacro("__TSXLDTRK__");

  if (HasUINTR)

    Builder.defineMacro("__UINTR__");

  if (HasCRC32)

    Builder.defineMacro("__CRC32__");



  // Each case falls through to the previous one here.

  switch (SSELevel) {
@@ -878,6 +888,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 
      .Case("clflushopt", true)

      .Case("clwb", true)

      .Case("clzero", true)

      .Case("crc32", true)

      .Case("cx16", true)

      .Case("enqcmd", true)

      .Case("f16c", true)
@@ -970,6 +981,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { 
      .Case("clflushopt", HasCLFLUSHOPT)

      .Case("clwb", HasCLWB)

      .Case("clzero", HasCLZERO)

      .Case("crc32", HasCRC32)

      .Case("cx8", HasCX8)

      .Case("cx16", HasCX16)

      .Case("enqcmd", HasENQCMD)