Commit 12454867 authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r300429:

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r300429 | d0k | 2017-04-16 16:13:08 -0400 (Sun, 16 Apr 2017) | 7 lines

[X86] Remove special handling for 16 bit for A asm constraints.

Our 16 bit support is assembler-only + the terrible hack that is
.code16gcc. Simply using 32 bit registers does the right thing for the
latter.

Fixes PR32681.
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llvm-svn: 301437
parent 39445ab0
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+3 −6
Original line number Diff line number Diff line
@@ -34722,14 +34722,11 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
      if (Subtarget.is64Bit()) {
        Res.first = X86::RAX;
        Res.second = &X86::GR64_ADRegClass;
      } else if (Subtarget.is32Bit()) {
      } else {
        assert((Subtarget.is32Bit() || Subtarget.is16Bit()) &&
               "Expecting 64, 32 or 16 bit subtarget");
        Res.first = X86::EAX;
        Res.second = &X86::GR32_ADRegClass;
      } else if (Subtarget.is16Bit()) {
        Res.first = X86::AX;
        Res.second = &X86::GR16_ADRegClass;
      } else {
        llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
      }
      return Res;
    }
+0 −1
Original line number Diff line number Diff line
@@ -438,7 +438,6 @@ def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
                                          (add LOW32_ADDR_ACCESS, RBP)>;

// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;

+8 −1
Original line number Diff line number Diff line
@@ -12,6 +12,13 @@ define i32 @main() #0 {
; CHECK: .code16
; CHECK-LABEL: main

define i64 @foo(i32 %index) #0 {
  %asm = tail call i64 asm "rdmsr", "=A,{cx},~{dirflag},~{fpsr},~{flags}"(i32 %index)
  ret i64 %asm
}

; CHECK-LABEL: foo
; CHECK: rdmsr

attributes #0 = { nounwind }