Loading llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +1 −8 Original line number Diff line number Diff line Loading @@ -1565,14 +1565,7 @@ HexagonTargetLowering::LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const { if (BitWidth == 64) return Combines[0]; // It must be i128. I128 is not a legal type, so this part will be // executed during type legalization. We need to generate code that // the default expansion can break up into smaller pieces. SDValue C0 = DAG.getZExtOrTrunc(Combines[0], dl, ResTy); SDValue C1 = DAG.getNode(ISD::SHL, dl, ResTy, DAG.getZExtOrTrunc(Combines[1], dl, ResTy), DAG.getConstant(64, dl, MVT::i32)); return DAG.getNode(ISD::OR, dl, ResTy, C0, C1); return DAG.getNode(ISD::BUILD_PAIR, dl, ResTy, Combines); } return Op; Loading Loading
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +1 −8 Original line number Diff line number Diff line Loading @@ -1565,14 +1565,7 @@ HexagonTargetLowering::LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const { if (BitWidth == 64) return Combines[0]; // It must be i128. I128 is not a legal type, so this part will be // executed during type legalization. We need to generate code that // the default expansion can break up into smaller pieces. SDValue C0 = DAG.getZExtOrTrunc(Combines[0], dl, ResTy); SDValue C1 = DAG.getNode(ISD::SHL, dl, ResTy, DAG.getZExtOrTrunc(Combines[1], dl, ResTy), DAG.getConstant(64, dl, MVT::i32)); return DAG.getNode(ISD::OR, dl, ResTy, C0, C1); return DAG.getNode(ISD::BUILD_PAIR, dl, ResTy, Combines); } return Op; Loading