Commit 0cf0be99 authored by Sanjay Patel's avatar Sanjay Patel
Browse files

[InstCombine] fix operands of shouldChangeType() for casted phi transform 

This is a bug noted in the recent D72733 and seen
in the similar transform just above the changed source code.

I added tests with illegal types and zexts to show the bug -
we could transform legal phi ops to illegal, etc. I did not add
tests with trunc because we won't see any diffs on those patterns.
That is because InstCombiner::SliceUpIllegalIntegerPHI() appears to
do those transforms independently of datalayout. It can also create
more casts than are present in existing code.

There are some existing regression tests that do not include a
datalayout that would be altered by this fix. I assumed that the
lack of a datalayout in those regression files is an oversight, so
I added the minimal layout (make i32 legal) necessary to preserve
behavior on those tests.

Differential Revision: https://reviews.llvm.org/D73907
parent 8c681f5e

llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ Instruction *InstCombiner::commonCastTransforms(CastInst &CI) { 
    // Don't do this if it would create a PHI node with an illegal type from a

    // legal type.

    if (!Src->getType()->isIntegerTy() || !CI.getType()->isIntegerTy() ||

        shouldChangeType(CI.getType(), Src->getType()))

        shouldChangeType(CI.getSrcTy(), CI.getType()))

      if (Instruction *NV = foldOpIntoPhi(CI, PN))

        return NV;

  }

llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll

+2 −0
Original line number Diff line number Diff line 
; RUN: llc -march=amdgcn -mcpu=gfx900 -print-after=si-annotate-control-flow %s -o /dev/null 2>&1 | FileCheck %s



target datalayout = "n32"



; CHECK-LABEL: @switch_unreachable_default



define amdgpu_kernel void @switch_unreachable_default(i32 addrspace(1)* %out, i8 addrspace(1)* %in0, i8 addrspace(1)* %in1) #0 {

llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll

+2 −0
Original line number Diff line number Diff line 
; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -amdgpu-lower-kernel-attributes -instcombine %s | FileCheck -enable-var-scope %s



target datalayout = "n32"



; CHECK-LABEL: @invalid_reqd_work_group_size(

; CHECK: load i16,

define amdgpu_kernel void @invalid_reqd_work_group_size(i16 addrspace(1)* %out) #0 !reqd_work_group_size !1 {

llvm/test/Transforms/InstCombine/cast_phi.ll

+9 −9
Original line number Diff line number Diff line
@@ -185,14 +185,14 @@ define i37 @zext_from_legal_to_illegal_type(i32 %x) { 
; CHECK-NEXT:    br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]

; CHECK:       t:

; CHECK-NEXT:    [[Y:%.*]] = call i32 @get_i32()

; CHECK-NEXT:    [[PHITMP:%.*]] = zext i32 [[Y]] to i37

; CHECK-NEXT:    br label [[EXIT:%.*]]

; CHECK:       f:

; CHECK-NEXT:    call void @bar()

; CHECK-NEXT:    br label [[EXIT]]

; CHECK:       exit:

; CHECK-NEXT:    [[P:%.*]] = phi i37 [ [[PHITMP]], [[T]] ], [ 3, [[F]] ]

; CHECK-NEXT:    ret i37 [[P]]

; CHECK-NEXT:    [[P:%.*]] = phi i32 [ [[Y]], [[T]] ], [ 3, [[F]] ]

; CHECK-NEXT:    [[R:%.*]] = zext i32 [[P]] to i37

; CHECK-NEXT:    ret i37 [[R]]

;

entry:

  %cmp = icmp eq i32 %x, 42
@@ -219,14 +219,14 @@ define i37 @zext_from_illegal_to_illegal_type(i32 %x) { 
; CHECK-NEXT:    br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]

; CHECK:       t:

; CHECK-NEXT:    [[Y:%.*]] = call i3 @get_i3()

; CHECK-NEXT:    [[PHITMP:%.*]] = zext i3 [[Y]] to i37

; CHECK-NEXT:    br label [[EXIT:%.*]]

; CHECK:       f:

; CHECK-NEXT:    call void @bar()

; CHECK-NEXT:    br label [[EXIT]]

; CHECK:       exit:

; CHECK-NEXT:    [[P:%.*]] = phi i37 [ [[PHITMP]], [[T]] ], [ 3, [[F]] ]

; CHECK-NEXT:    ret i37 [[P]]

; CHECK-NEXT:    [[P:%.*]] = phi i3 [ [[Y]], [[T]] ], [ 3, [[F]] ]

; CHECK-NEXT:    [[R:%.*]] = zext i3 [[P]] to i37

; CHECK-NEXT:    ret i37 [[R]]

;

entry:

  %cmp = icmp eq i32 %x, 42
@@ -287,14 +287,14 @@ define i64 @zext_from_illegal_to_legal_type(i32 %x) { 
; CHECK-NEXT:    br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]

; CHECK:       t:

; CHECK-NEXT:    [[Y:%.*]] = call i3 @get_i3()

; CHECK-NEXT:    [[PHITMP:%.*]] = zext i3 [[Y]] to i64

; CHECK-NEXT:    br label [[EXIT:%.*]]

; CHECK:       f:

; CHECK-NEXT:    call void @bar()

; CHECK-NEXT:    br label [[EXIT]]

; CHECK:       exit:

; CHECK-NEXT:    [[P:%.*]] = phi i3 [ [[Y]], [[T]] ], [ 3, [[F]] ]

; CHECK-NEXT:    [[R:%.*]] = zext i3 [[P]] to i64

; CHECK-NEXT:    ret i64 [[R]]

; CHECK-NEXT:    [[P:%.*]] = phi i64 [ [[PHITMP]], [[T]] ], [ 3, [[F]] ]

; CHECK-NEXT:    ret i64 [[P]]

;

entry:

  %cmp = icmp eq i32 %x, 42

llvm/test/Transforms/InstCombine/icmp-div-constant.ll

+2 −0
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py

; RUN: opt < %s -instcombine -S | FileCheck %s



target datalayout = "n32"



define i1 @is_rem2_neg_i8(i8 %x) {

; CHECK-LABEL: @is_rem2_neg_i8(

; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], -127