Commit 0b1d2467 authored by Bill Wendling's avatar Bill Wendling
Browse files

Merging r155902: 

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r155902 | void | 2012-05-01 01:27:43 -0700 (Tue, 01 May 2012) | 7 lines

Change the PassManager from a reference to a pointer.

The TargetPassManager's default constructor wants to initialize the PassManager
to 'null'. But it's illegal to bind a null reference to a null l-value. Make the
ivar a pointer instead.
PR12468

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llvm-svn: 155903
parent 26951d3d

llvm/include/llvm/CodeGen/Passes.h

+1 −1
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ public: 


protected:

  TargetMachine *TM;

  PassManagerBase ±

  PassManagerBase *PM;

  PassConfigImpl *Impl; // Internal data structures

  bool Initialized;     // Flagged after all passes are configured.

llvm/lib/CodeGen/Passes.cpp

+21 −21
Original line number Diff line number Diff line
@@ -207,7 +207,7 @@ TargetPassConfig::~TargetPassConfig() { 
// Out of line constructor provides default values for pass options and

// registers all common codegen passes.

TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)

  : ImmutablePass(ID), TM(tm), PM(pm), Impl(0), Initialized(false),

  : ImmutablePass(ID), TM(tm), PM(&pm), Impl(0), Initialized(false),

    DisableVerify(false),

    EnableTailMerge(true) {
@@ -234,7 +234,7 @@ TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { 
}



TargetPassConfig::TargetPassConfig()

  : ImmutablePass(ID), PM(*(PassManagerBase*)0) {

  : ImmutablePass(ID), PM(0) {

  llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");

}
@@ -269,16 +269,16 @@ AnalysisID TargetPassConfig::addPass(char &ID) { 
  Pass *P = Pass::createPass(FinalID);

  if (!P)

    llvm_unreachable("Pass ID not registered");

  PM.add(P);

  PM->add(P);

  return FinalID;

}



void TargetPassConfig::printAndVerify(const char *Banner) const {

  if (TM->shouldPrintMachineCode())

    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));

    PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));



  if (VerifyMachineCode)

    PM.add(createMachineVerifierPass(Banner));

    PM->add(createMachineVerifierPass(Banner));

}



/// Add common target configurable passes that perform LLVM IR to IR transforms
@@ -288,46 +288,46 @@ void TargetPassConfig::addIRPasses() { 
  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that

  // BasicAliasAnalysis wins if they disagree. This is intended to help

  // support "obvious" type-punning idioms.

  PM.add(createTypeBasedAliasAnalysisPass());

  PM.add(createBasicAliasAnalysisPass());

  PM->add(createTypeBasedAliasAnalysisPass());

  PM->add(createBasicAliasAnalysisPass());



  // Before running any passes, run the verifier to determine if the input

  // coming from the front-end and/or optimizer is valid.

  if (!DisableVerify)

    PM.add(createVerifierPass());

    PM->add(createVerifierPass());



  // Run loop strength reduction before anything else.

  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {

    PM.add(createLoopStrengthReducePass(getTargetLowering()));

    PM->add(createLoopStrengthReducePass(getTargetLowering()));

    if (PrintLSR)

      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));

      PM->add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));

  }



  PM.add(createGCLoweringPass());

  PM->add(createGCLoweringPass());



  // Make sure that no unreachable blocks are instruction selected.

  PM.add(createUnreachableBlockEliminationPass());

  PM->add(createUnreachableBlockEliminationPass());

}



/// Add common passes that perform LLVM IR to IR transforms in preparation for

/// instruction selection.

void TargetPassConfig::addISelPrepare() {

  if (getOptLevel() != CodeGenOpt::None && !DisableCGP)

    PM.add(createCodeGenPreparePass(getTargetLowering()));

    PM->add(createCodeGenPreparePass(getTargetLowering()));



  PM.add(createStackProtectorPass(getTargetLowering()));

  PM->add(createStackProtectorPass(getTargetLowering()));



  addPreISel();



  if (PrintISelInput)

    PM.add(createPrintFunctionPass("\n\n"

    PM->add(createPrintFunctionPass("\n\n"

                                    "*** Final LLVM Code input to ISel ***\n",

                                    &dbgs()));



  // All passes which modify the LLVM IR are now complete; run the verifier

  // to ensure that the IR is valid.

  if (!DisableVerify)

    PM.add(createVerifierPass());

    PM->add(createVerifierPass());

}



/// Add the complete set of target-independent postISel code generator passes.
@@ -405,7 +405,7 @@ void TargetPassConfig::addMachinePasses() { 
  // GC

  addPass(GCMachineCodeAnalysisID);

  if (PrintGCInfo)

    PM.add(createGCInfoPrinter(dbgs()));

    PM->add(createGCInfoPrinter(dbgs()));



  // Basic block placement.

  if (getOptLevel() != CodeGenOpt::None)
@@ -522,7 +522,7 @@ void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { 
  addPass(PHIEliminationID);

  addPass(TwoAddressInstructionPassID);



  PM.add(RegAllocPass);

  PM->add(RegAllocPass);

  printAndVerify("After Register Allocation");

}
@@ -564,7 +564,7 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { 
    printAndVerify("After Machine Scheduling");



  // Add the selected register allocation pass.

  PM.add(RegAllocPass);

  PM->add(RegAllocPass);

  printAndVerify("After Register Allocation");



  // FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,

llvm/lib/Target/ARM/ARMTargetMachine.cpp

+10 −10
Original line number Diff line number Diff line
@@ -136,22 +136,22 @@ TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) { 


bool ARMPassConfig::addPreISel() {

  if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)

    PM.add(createGlobalMergePass(TM->getTargetLowering()));

    PM->add(createGlobalMergePass(TM->getTargetLowering()));



  return false;

}



bool ARMPassConfig::addInstSelector() {

  PM.add(createARMISelDag(getARMTargetMachine(), getOptLevel()));

  PM->add(createARMISelDag(getARMTargetMachine(), getOptLevel()));

  return false;

}



bool ARMPassConfig::addPreRegAlloc() {

  // FIXME: temporarily disabling load / store optimization pass for Thumb1.

  if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())

    PM.add(createARMLoadStoreOptimizationPass(true));

    PM->add(createARMLoadStoreOptimizationPass(true));

  if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())

    PM.add(createMLxExpansionPass());

    PM->add(createMLxExpansionPass());

  return true;

}
@@ -159,23 +159,23 @@ bool ARMPassConfig::addPreSched2() { 
  // FIXME: temporarily disabling load / store optimization pass for Thumb1.

  if (getOptLevel() != CodeGenOpt::None) {

    if (!getARMSubtarget().isThumb1Only()) {

      PM.add(createARMLoadStoreOptimizationPass());

      PM->add(createARMLoadStoreOptimizationPass());

      printAndVerify("After ARM load / store optimizer");

    }

    if (getARMSubtarget().hasNEON())

      PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass));

      PM->add(createExecutionDependencyFixPass(&ARM::DPRRegClass));

  }



  // Expand some pseudo instructions into multiple instructions to allow

  // proper scheduling.

  PM.add(createARMExpandPseudoPass());

  PM->add(createARMExpandPseudoPass());



  if (getOptLevel() != CodeGenOpt::None) {

    if (!getARMSubtarget().isThumb1Only())

      addPass(IfConverterID);

  }

  if (getARMSubtarget().isThumb2())

    PM.add(createThumb2ITBlockPass());

    PM->add(createThumb2ITBlockPass());



  return true;

}
@@ -183,13 +183,13 @@ bool ARMPassConfig::addPreSched2() { 
bool ARMPassConfig::addPreEmitPass() {

  if (getARMSubtarget().isThumb2()) {

    if (!getARMSubtarget().prefers32BitThumb())

      PM.add(createThumb2SizeReductionPass());

      PM->add(createThumb2SizeReductionPass());



    // Constant island pass work on unbundled instructions.

    addPass(UnpackMachineBundlesID);

  }



  PM.add(createARMConstantIslandPass());

  PM->add(createARMConstantIslandPass());



  return true;

}

llvm/lib/Target/CellSPU/SPUTargetMachine.cpp

+3 −3
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) { 


bool SPUPassConfig::addInstSelector() {

  // Install an instruction selector.

  PM.add(createSPUISelDag(getSPUTargetMachine()));

  PM->add(createSPUISelDag(getSPUTargetMachine()));

  return false;

}
@@ -85,9 +85,9 @@ bool SPUPassConfig::addPreEmitPass() { 
    (BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(

          "createTCESchedulerPass");

  if (schedulerCreator != NULL)

      PM.add(schedulerCreator("cellspu"));

      PM->add(schedulerCreator("cellspu"));



  //align instructions with nops/lnops for dual issue

  PM.add(createSPUNopFillerPass(getSPUTargetMachine()));

  PM->add(createSPUNopFillerPass(getSPUTargetMachine()));

  return true;

}

llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp

+8 −8
Original line number Diff line number Diff line
@@ -100,23 +100,23 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { 
}



bool HexagonPassConfig::addInstSelector() {

  PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));

  PM.add(createHexagonISelDag(getHexagonTargetMachine()));

  PM.add(createHexagonPeephole());

  PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));

  PM->add(createHexagonISelDag(getHexagonTargetMachine()));

  PM->add(createHexagonPeephole());

  return false;

}





bool HexagonPassConfig::addPreRegAlloc() {

  if (!DisableHardwareLoops) {

    PM.add(createHexagonHardwareLoops());

    PM->add(createHexagonHardwareLoops());

  }



  return false;

}



bool HexagonPassConfig::addPostRegAlloc() {

  PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));

  PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));

  return true;

}
@@ -129,14 +129,14 @@ bool HexagonPassConfig::addPreSched2() { 
bool HexagonPassConfig::addPreEmitPass() {



  if (!DisableHardwareLoops) {

    PM.add(createHexagonFixupHwLoops());

    PM->add(createHexagonFixupHwLoops());

  }



  // Expand Spill code for predicate registers.

  PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));

  PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));



  // Split up TFRcondsets into conditional transfers.

  PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));

  PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));



  return false;

}