Commit 0abd0b2d authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r214865: 

------------------------------------------------------------------------
r214865 | thomas.stellard | 2014-08-05 10:40:52 -0400 (Tue, 05 Aug 2014) | 5 lines

R600/SI: Avoid generating REGISTER_LOAD instructions.

SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code
path for 8-bit and 16-bit private loads.

------------------------------------------------------------------------

llvm-svn: 214895
parent 3e548d31

llvm/lib/Target/R600/AMDGPUISelLowering.cpp

+2 −1
Original line number Diff line number Diff line
@@ -1176,7 +1176,8 @@ SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 
    return DAG.getMergeValues(Ops, DL);

  }



  if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||

  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||

      Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||

      ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))

    return SDValue();

llvm/test/CodeGen/R600/private-memory.ll

+2 −1
Original line number Diff line number Diff line
@@ -118,7 +118,8 @@ for.end: 


; SI-PROMOTE: BUFFER_STORE_SHORT v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s{{[0-9]+}}

; SI-PROMOTE: BUFFER_STORE_SHORT v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s{{[0-9]+}}

; SI_PROMOTE: BUFFER_LOAD_SSHORT v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] + v{{[0-9]+}}, s{{[0-9]+}}

; SI-PROMOTE-NOT: MOVREL

; SI-PROMOTE: BUFFER_LOAD_SSHORT v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] + v{{[0-9]+}} + s{{[0-9]+}}

define void @short_array(i32 addrspace(1)* %out, i32 %index) {

entry:

  %0 = alloca [2 x i16]